Toshiba to promote MeP core with tool vendors, design houses

Toshiba said it will provide the infrastructure for a comprehensive design flow that gives customers the option of using the configurable MeP processor independent of Toshiba. Some foundries have also agreed to promote MeP, according to Toshiba.

"The wide range of partners and the comprehensive development flow will be offered through a portal site," said Jan Goodsell, president of CoWare's Japanese unit.

Toshiba announced the MeP architecture in April 2002 and has developed core-based ASSP devices such as an MPEG-2 decoder and application processor for mobile phones. From the start, Toshiba intended to offer the processor core as IP in hopes of making it a de facto standard embedded processor for multimedia applications. It also hopes to sell MeP-based SoCs.

Toshiba has also been preparing a design environment involving third parties to promote the processor core.

The MeP core includes Toshiba's configurable, 32-bit RISC architecture. It employs a set of 65 basic instructions, 16 and 32-bit variable instruction lengths and has 16 general-purpose registers and a five-stage pipeline.

The processor was fabricated on a 0.13-micron process. MeP-C2, or version two, has the minimum configuration of 46K gates, operates at 200 MHz in the worst case with 2-Kbyte 1-cache and 16 Kbyte data RAM consuming 0.11 mW per MHz.

Depending on the application, the processor core can be configured choosing options such as instructions, memory configuration, a debug support option, interrupt controller timer/counter and bus interface width. Toshiba claimed the MeP core and pre-prepared extensions — hardware and software IPs — are designed to form MeP modules that achieve optimum functions for specific applicationa. Options such as customized instructions, DSP unit, hardware engines and a VLIW (very long instruction word) co-processor are also offered. Multiple MeP modules with different functions such as video and audio decoding are connected to a global data bus to form an SoC.

Toshiba developed a C3 version of its MeP core last year with enhanced DSP functionality. Toshiba jointly worked with Elixent to add reconfigurability. The MeP roadmap includes a higher-performance H1 version with increased pipelines and a C4 version planned for later this year.

Toshiba has a three-part business strategy for MeP cores: sales of MeP core ASICs, licensing of MeP IP and offering MeP IPs through the Web portal. In addition to its own sales, Toshiba wants to promote the core as a de facto standard through its partners.

The MeP core will also work with the Sony's Cell processor. "By combining a Cell processor as a host and MeP for multimedia application processing, the combination should increase performance and meet wider applications," said Toshinori Moriyasu, executive vice president of Toshiba Semiconductor.

The MeP promotion will initially focus on the Japanese market, beginning with MeP World 2004 here in August. It will extend overseas through a MeP User Forum in October in San Jose, Calif.

Toshiba's announced MeP partners are: Advanced Data controls, Sophia Systems, RedHat Inc., who will provide software development tools; InterDesign technologies, Pacific Design, Celoxica Ltd., CoWare Inc., providing tools for high-level design; Synopsys Inc., which will provide logic design tools; Oki Network LSI, Cdex and Dai Nippon Printing Co. Ltd., who will offer design services; and Sonics, Inc., who will supply provide IP for MeP SoCs.