Update: Aplus Flash Technology is no more in business
San Jose , CA, June 4, 2004 – Aplus Flash Technology has introduced an improved version of its silicon proven 0.35um 2P3M CMOS based OTP EPROM IP suitable for low voltage operations down to 1.8V. This product represents Aplus’ most advanced line of OTP EPROM IP. Aplus’ 0.5um 2P2M OTP IP has already been in stable, high-yield production at various foundries worldwide for many years.
OTP EPROM requires ultraviolet (UV) light for erasing operations. As the process technology shrinks to smaller geometries, the ability to erase uniform cells becomes more difficult. While flash memory technology has been scaled below0.13um process technology, OTP EPROM memory can not be scaled below 0.35um.
Although some companies currently offer a logic-based 0.35um OTP that uses a less mature single poly process, Aplus’ 0.35um OTP is based on a traditional double poly process. Aplus’ 2P OTP has cell size of about 10.7 ë2, while a single poly OTP process has a cell size of ~37 ë2. Single poly OTP does not have equivalent years of production data of double poly OTP. Aplus is the first company to offer 0.35um OTP EPROM IP that uses a mature, traditional, double poly CMOS process that has been silicon proven with high, stable yields and high data retention rate of over 10 years.
| ||Aplus' 0.35um 2P EMBEDDED OTP IP ||Typical 0.35um 1P EMBEDDED OTP ||Remarks |
|Cell Size ||~10.7ë2 ||~37ë2 || |
|64KB Block Size ||1.6mm2 ||3.4mm2 || |
|Data Retention ||10 yrs (from historical production data) ||N/A || |
|Years in Production ||>20 years ||Recently introduced, no data available || |
|Vdd range ||1.8V - 3.6V available ||2.7V - 3.3V || |
|Mask Layers ||Polycide - 22, Silicide - 23 ||18 - Polycide, 19 - Silicide || |
|Die Cost Comparison ||1X ||1.75X ||Not considering size of CPU & other chip circuitry |
|Other technologies using same number of poly in high volume production ||NAND, NOR, EEPROM ||ROM || |
Embedded OTP is suitable for a wide variety of computing, communications and consumer applications. Aplus’ OTP IP can be found embedded in applications such as speech synthesis and recognition, LCD drivers, consumer appliance microcontrollers, cellular and wireless applications, and many more ASICs, DSPs and MCUs.
“Our 0.35um OTP IP offers an answer to companies looking for a low-cost flash alternative or an upgrade solution for ROM in their ICs. As the cost of OTP decreases, the benefits of having an externally programmable chip to reduce inventory becomes more attractive. We have a lot of customers asking for OTP for both of these reasons. As a proven leader in 0.5um process technology, we are happy to offer our customers the same high-quality IP in 0.35um for further cost savings. This OTP technology also provides an opportunity to many of our customers that need a cost-effective alternative to their 0.35um flash solutions,” states Dr. Henry Ma , VP of Business Development at Aplus.
Aplus 0.35um OTP IP* offers:
- Wide operating voltage range from 1.8V – 3.6V**
- Low read current: ~4mA typical @ 4MHz read cycle
- Low standby current: <10uA typical
- Fast read access times: ~ 80ns @ 3V
- Fast program time: ~60us per word (16-bit)
- Small cell size: ~10ë2
- Small block size
- Industrial temperature range: -40 to 85C
- 10-year data retention
- 22 layers based on 0.35um 2P3M CMOS technology
*Data measured on OTP EPROM IP with density of 2Mbits
**Working Vdd range can be increased to 1.8 - 5.5V as a customized design
“ Note: Product Information is subject to change and update. The Company has no obligation to update the forward-looking information or product information contained in this release."
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