Xilinx rolls soft core 32-bit MPU, eyes networking
Xilinx rolls soft core 32-bit MPU, eyes networking
By Michael Santarini, EE Times
April 9, 2001 (10:19 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010409S0021
By releasing its MicroBlaze 32-bit processor this week at the Embedded Systems Conference (San Francisco), Xilinx Inc. is diligently laying the groundwork for a new multiprocessor platform that it expects to complete when the company's Virtex Pro PowerPC device ultimately rolls.
At 125 MHz, with a 32-bit instruction and data bus, the MicroBlaze soft processor core is fast, said Mark Aaldering, senior director of intellectual-property solutions at Xilinx. It can be implemented as a standalone processor in Spartan II or Virtex FPGAs, he said. But since it consumes 800 lookup tables, the core can also be mixed and matched with additional MicroBlaze processors and peripherals on Virtex devices to create a multiprocessor platform.
The big payoff for Xilinx will come with the release of the Virtex Pro PowerPC core. The company envisions adding MicroBlaze MPU cores and MicroBlaze peripherals to the Virtex Pro PowerPC to create a high-performanc e, multiprocessor platform "supremely" suited for networking, telecommunication, data communication, embedded and consumer markets, said Babak Hedayati, director of marketing and business development.
Aaldering said the MicroBlaze uses IBM's CoreConnect bus for peripherals-the same bus used for the embedded PowerPC. This, he said, will let Xilinx and other developers create peripherals that work with PowerPC alone, MicroBlaze alone or the two together on a Virtex Pro PowerPC. Xilinx has already delivered arbiter and UART CoreConnect-enabled peripherals to beta partners.
Using a Harvard-style architecture, MicroBlaze has separate 32-bit instruction and data buses running at full speed to execute programs or access data from on-chip or external memory, Aaldering said. The processor is implemented in 50 D-Mips using the Dhrystone benchmarks, with a road map to 75 D-Mips by late summer and 100 D-Mips next year.
MicroBlaze and the larger platform concept have won the support of Wind River Systems via that company's WindLink partners program, Aaldering said.
The device is due to reach production in late summer. The MicroBlaze development kit, which includes core, peripherals and a set of GNU-based software tools including compiler, assembler and debugger, will be priced at $495. Variations of the kit will include a Virtex-II development board and FPGA design tools. For details, visit www.xilinx.com.
---
Innovative Semiconductors Inc. (Santa Clara, Calif.) is aiming its USB 2.0 device controller core at computer and consumer peripheral products. The SL250 complies with USB 2.0 and has been verified in the ISD-300 bridge.
Together with the SL200 USB 2.0 mixed-signal transceiver macrocell, the new core provides Innovative's customers with all the building blocks necessary to build USB 2.0 peripherals, the company said. The USB serial bus boasts real-time data transfer at up to 480 Mbits/second. The SL250 is available in synthe sizable RTL and includes a comprehensive testbench, validation suite, synthesis scripts and user documentation. The analog front end is process-technology-specific and available in 0.25- and 0.18-micron digital CMOS processes. Visit www.isi96.com for more information.
Related News
- Xilinx Spartan-3 FPGAs Deliver 32-Bit MicroBlaze Soft Processor for Less Than 75 Cents
- Freescale Paves the Way for Autonomous Vehicles with Industry's First 32-Bit Flash-Based Microcontroller with FlexRay(TM); Integration of Networking Protocol with PowerPC(R) Core Targets High-End Powertrain and Chassis Applications
- MIPS Technologies Licenses 32-Bit Core to Proxim for Use in High-Speed Wireless Networking Products
- Xilinx Extends its Lead in PCI Market With Complete 64- and 32-bit Solutions Below ASSP Prices
- Centillium rolls out processor for voice-enabled broadband systems based on a 32-bit RISC core from Mips Technologies Inc.
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |