Denali Joins Synopsys SystemVerilog Catalyst Program
Details Of SystemVerilog Support To Be Unveiled At Accellera's Lunch Event At DAC
PALO ALTO, Calif. -- June 7, 2004 -- Denali Software today announced that it has joined the Synopsys SystemVerilog Catalyst program. The industry program is designed to speed support of SystemVerilog by electronic design automation (EDA) vendors, verification intellectual property (IP) suppliers, and training service providers to ensure designers' success with SystemVerilog. By joining the SystemVerilog Catalyst program, Denali will utilize the program framework to extend its verification IP products and methodologies to support the SystemVerilog hardware description and verification language.
In addition, Denali will be presenting details of its support for SystemVerilog at Accellera's SystemVerilog: Right Here! Right Now! lunch event held at the 41st Design Automation Conference (DAC) Tuesday, June 8, in Room 29 of the San Diego Convention Center, San Diego, Calif. This SystemVerilog event is accessible to all DAC attendees.
"Our goal is to deliver the highest quality verification IP to our customers, and ensure a seamless integration with other state-of-the-art design and verification methodologies," said Kevin Silver, vice president of marketing for Denali. "There is great momentum behind SystemVerilog, and our customers are now entering the adoption phase. We believe that by supporting SystemVerilog with our PureSpec verification IP product portfolio, especially for PCI Express, our customers will see significant overall design and verification productivity improvements."
"We welcome Denali as the most recent member of the Synopsys SystemVerilog Catalyst Program, which is continuing to grow with over 50 vendors," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "The demand for SystemVerilog from the design community is obvious based on the enthusiastic and overwhelming support for the language by the vast majority of the EDA and IP industry. Denali's strong commitment to SystemVerilog benefits designers through faster and more unified verification."
About PureSpec
PureSpec is the most widely used verification IP product for simulating and verifying PCI Express design interfaces. PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all protocol layers (physical, data link, transaction) of the PCI Express specification are completely modeled and can be simulated concurrently or independently. The product contains thousands of assertions that are monitored during simulation to ensure compliance with the PCI Express specification and interoperability with other PCI Express devices. The PureSpec product provides seamless integrations to all popular EDA tools and verification languages. The PureSpec product is available now for customer evaluation at: www.denali.com/purespec.
About Denali Software, Inc.
Denali Software Inc. is a leading provider of electronic design automation (EDA) software and Intellectual Property (IP) solutions for chip interface design, integration, and verification. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. Corporate headquarters are located at: 1850B Embarcadero Road, Palo Alto, Calif. 94303. For more information, visit Denali at www.denali.com. Or, contact Denali by phone at: (650) 461-7200, or email: info@denali.com.
Denali, the Denali logo, Databahn, eMemory, MMAV, and PureSpec are trademarks of Denali Software Inc. PCI Express is a registered trademark of PCI-SIG. All other registered trademarks and other trademarks that may be mentioned in this release belong to their respective owners.
|
Related News
- Synopsys Launches SystemVerilog Catalyst Program
- ADTechnology Joins Synopsys IP OEM Partner Program
- Synopsys Joins GLOBALFOUNDRIES' FDXcelerator Partner Program to Enable Innovative Designs Using the FD-SOI Process
- Open-Silicon Joins Synopsys ARC Access Program
- Synopsys Enables System Design Interoperability With System-Level Catalyst Program
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
E-mail This Article | Printer-Friendly Page |