TriDL™ Architecture Enables Industry Leading Power and Area Efficiencies SAN FRANCISCO, CA
- June 7, 2004
- TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, today announced the immediate availability of the most area and power-efficient PCI-Express PHYs in the industry. Incorporating the company's patented and silicon-proven TriDL™
digital sampling SerDes architecture, TriCN's PCI-Express PHYs support all lane configurations, including X1, X2, X4, X8, X12, X16, and X32, and are available in the TSMC 130nm process.
TriCN's PCI-Express PHYs incorporate a two-tiered configuration approach towards the highly scalable PCI-Express interface technology. The first is a true X1 lane configuration that allows for the most efficient design possible for companies striving to minimize area and power (such as consumer product applications). This is a departure from many competing offerings that disable multi-lane PHYs, which penalize customers with unnecessary overhead. For multi-lane configurations, TriCN employs a scalable multi-lane design architecture starting with a X4 implementation and scaling to a X32. With the addition of multiple lanes, the TriDL digital sampling technology enables significant area and power gains versus comparable analog designs, while also providing exceptionally reliable data transmission across the link.
"With today's announcement, semiconductor designers now have a critically important arsenal of IP that enables them to optimize the performance and reliability of PCI-Express interfaces for new chips being introduced in networking, communications and consumer market segments," said Ron Nikel, co-founder and Chief Technology Officer of TriCN. "As high-performance interface specialists, TriCN is uniquely qualified to deliver the industry's most efficient PCI-Express PHY design. These PHYs embody what we hear as a clear requirement from the market; area and power efficiencies, coupled with rock-solid data transmission technology."
TriCN PCI-Express PHYs are PIPE 1.0a compliant, and include the SerDes, the PIPE logic and the I/Os. The products are delivered as a hard macro requiring no further RTL synthesis, significantly reducing engineering time and risk over comparable solutions with soft IP components. The TriCN PCI-Express PHYs support lane reversal, per lane at speed internal loop back BIST, 20ns RX deskewing, and both 250MHz/8 bit per lane and 125 MHz/10 bit per lane native interfaces. TriCN's TriDL Technology
TriDL (Digital Dynamic Deskewing Logic) provides the base architecture for TriCN's PHYs, including PCI-Express. TriDL is an all-digital sampling technology that is unique in the semiconductor industry. The all-digital approach not only provides savings in area and power usage, but also streamlines porting and testability, and offers increased noise immunity not found in analog based devices. Availability
TriCN's PCI Express PHY products are immediately available in the TSMC 130nm process.About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. All products are designed using rigorous signal integrity and timing analysis to ensure first time power-up success. Products include Base I/O libraries for pad-ring creation, high-performance memory and networking interfaces, multi-function I/O's compatible with multiple interface protocols, and multi-gigabit PHY products. TriCN's customers range from fabless semiconductor to systems companies and IDMs.