NEC engineers advance hardware/software co-verification

![]() ![]() | |
EE Times: Latest News NEC engineers advance hardware/software co-verification | |
Yoshiko Hara (06/11/2004 7:00 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=21700502 | |
SAN DIEGO — Claiming a new approach to hardware/software co-verification, researchers from NEC presented details about a combined simulation and emulation system at a Design Automation Conference paper session here. The approach integrates a C++ simulator with a low-cost FPGA-based emulator using shared register communications. "Such combined systems already exist, but the strong point of our system is that every step of a program's execution completely synchronizes between the simulator and the emulator," said Yuichi Nakamura, principal researcher of multimedia architecture technology group at NEC's Media and Information Research laboratories. "It's important that the verification system behave the same way as the actual device does," said Nakamura. He noted that RTL simulators are expensive but slow, while commercial FPGA-based emulation systems can cost millions of dollars. If a program runs in one second on an actual device with 100 MHz clock, it takes about 2 minutes for the same program to run on an FPGA emulator operating at 1 MHz, and it takes about 100 days on a RTL simulator operating at 10 kHz. C/C++ simulators are between RTL simulators and FPGA emulators in terms of speed but are inferior in accuracy, according to NEC. NEC engineers combined a PC-based C/C++ simulator that works at about 100 kHz with a small-scale FPGA emulator that costs a few tens of thousands of dollars. NEC engineers say the combined system is as accurate as RTL simulation but is about 1,000 times faster. The PC simulator and the FPGA are connected by shared communication registers, which correspond to a bus in actual device. The register array is implemented on the FPGA emulator. The registers make it possible to send an instruction from the PC simulator and to receive a response to the instruction from the FPGA emulator in the same system cycle. Lines of code can be executed one at a time, with the emulator returning a value at every step. "At whatever point a bug occurs, we can stop the execution on the spot and check the cause," said Nakamura. NEC has been developing the verification system since 2000. The system was used to develop NEC Electronics' LSIs for DVD recorders. "The embedded software developed prior to the device fabrication run on the devices at once without any bugs," said Nakamura. The verification system lets designers develop embedded software in parallel with hardware design, without waiting for the actual device being fabricated and becoming available, he said. NEC Electronics intends to introduce about 50 of these verification systems internally by autumn this year. NEC also intends to make it available to its customers who want to develop embedded software by themselves. "Our support resources are limited, so the system will be available only to our customers for the time being," said Nakamura.
| |
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | |

Related News
- Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models
- Quickturn Announces IP Program to Provide High-Speed Hardware/Software Co-Verification Environment for SoC Designs
- Synopsys and Hitachi Deliver First Hardware/Software Co-Verification Models for SH3-DSP and SH-4 Processor Cores
- Endeavor Intertech Corporation to Provide Accurate High Performance Models of Complex Cores for Synopsys Eaglei Hardware-Software Co-Verification Environment
- EVE Ends Calendar Year 2008 with More Than 30% Year-to-Year Growth, Consolidating Worldwide Hardware/Software Co-Verification Leadership Position
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |