Crolles alliance rolls 65-nm process

The process cuts the SRAM cell size in half, to 0.5 microns², compared with the 90-nm process, keeping the partners on the beneficial Moore's Law curve of reduced cost per function.

"The strong point of the 65-nm process," said Franck Arnaud, ST's manager of CMOS process integration, "is that it does not require any breakthroughs" in terms of new materials such as the copper wiring or low-k dielectrics. These caused problems for many companies at the 130- and 90-nm generations.

The Crolles 65-nm process, for example, uses the same low-k dielectric — Black Diamond CVD material from Applied Materials — that the partners used at the 90-nm node. At the second stage, the partners will move to a more advanced carbon-doped oxide with a k-value of 2.5.

With no new materials to prove out, Arnaud said the process "will be available on the market early, with a gain in density and enhanced performance." The high-performance flavor, with a shorter gate length than the low-power or general-purpose versions, will deliver a 20 percent enhancement in transistor performance, albeit with more current leakage, he said.

The partners earlier co-developed a baseline 90-nm process at the Crolles, France, development center. ST plans to move the 65-nm process into "risk production" in the third quarter of 2005, Arnaud said, with several high-volume customers beginning designs this year.

The shift to a high-k dielectric at the critical gate insulation layer will come later, at the 45-nm node, perhaps in tandem with metal gate electrodes.

Arnaud said the major technical challenge at the 65-nm node came in the lithography steps, particularly development of the optical proximity correction (OPC) enhancements to the dry, or non-immersion, 193-nm scanners. The partners may introduce immersion lithography in the 2005-06 time frame, or as soon as the "wet" 193-nm tools become available, he added.

The process developed is identical among the three partners. It also is aligned with the 65-nm process being developed at Taiwan Semiconductor Manufacturing Co. (TSMC), which is an auxiliary member of the Crolles alliance. The transistor targets, including electrical specifications such as the on- and off-current, are the same among the three Crolles partners and TSMC's 65-nm process. The digital Spice models are identical, Arnaud said, though the mixed signal and other non-digital models differ.

The 65-nm process enhances the process-induced strain techniques first employed at the 90-nm node to improve electron and hole mobilities in the NMOS and PMOS devices. Arnaud estimated that strain provided a 20-30 gain in mobility, which results in a 10 to 20 percent increase in current drive in saturation mode.

One major challenge at the 65-nm node is to keep power consumption under control, Arnaud said. The general-purpose 65-nm process includes a high threshold voltage flavor that runs at an operating voltage of 0.9 V, with an oxide thickness of 13 Angstroms and a gate length of 45-nm.

For low-power applications, the gate length remains at 60-nm, the gate insulation layer is much thicker and designers can implement source and drain bias techniques without pump charge circuits to reduce power. Also, designers can put the SRAM blocks into sleep mode, and add voltage islands at the customer's discretion, he added.

The power consumption depends in part on the temperature of the chip in operation. High-performance ICs tend to run in hot operating environments, where leakage is higher. General-purpose products, optimized for cost, usually work in room-temperature environments, and current leakage is slightly worse at the 65-nm node than for 90 nm. The low-power process has identical or slightly better power metrics than the 90-nm process, though the performance gain ranges from zero to 10 percent, he said.