LSI Logic Announces QDR-2 SRAM Memory Interfaces for Developing High-End Network and Storage Gear

• Industry's highest speed QDR-2 memory interfaces with HSTL I/O buffers enable faster and easier product development
• Pre-verified interface solution closes timing at double-data rate, significantly reducing development risk and speeding time to market

MILPITAS, Calif. June 29, 2004 LSI Logic Corporation (NYSE: LSI) today introduced the industrys highest speed physical layer interface to QDR-2 SRAM memory, enabling the next generation of high-end network routers, switches and host bus adapters. Supporting speeds up to 333MHz/667Mbps, the new QDR-2 ASIC core makes it easy for network equipment manufacturers to tap the low latency, high bandwidth capabilities of QDR-2 SRAM for designing terabit-level products with shorter development times.

LSI Logics QDR-2 core is a physical layer interface with a special HSTL I/O interface buffer that can be easily integrated on a cell-based ASIC, or a RapidChipTMPlatform ASIC for fast system-on-a-chip (SoC) designs. The QDR-2 is a pre-verified physical layer interface validated in silicon, which significantly reduces the risk and turnaround time of product development.
QDR-2 SRAMs are ideal for the high-bandwidth, latency-sensitive applications of terabit-speed telecom and data network gear, said Jean Bou-Farhat, vice president, CoreWare, LSI Logic. But these high performance memories present new challenges in designing and implementing the physical layer interfaces. The QDR-2 core is designed to speed the implementation with ease and complete confidence in a solution that has been tested and validated in silicon.

LSI Logics QDR-2 cores includes address and data path hardmacros with HSTL I/O buffers and provides an integration-friendly physical layer interface between a customers ASIC memory controller logic and the data and address busses of QDR-SRAM memory. The core and I/O are available in LSI Logics GflxTMprocess technology (0.11um) and can operate at data rates up to 667Mbps. The READ and WRITE data paths are 18 bits wide and can be used in parallel to build data bus widths of 18 bits, 36 bits or 72 bits providing a total bandwidth of 24 Gbps, 48 Gbps and 96 Gbps respectively. The address hardmacro is 22 bits wide. If an application requires more address bits, then multiple address hardmacros may be used.

The QDR-2 core employs hardmacros with pre-verified functionality, layout and guaranteed timing closure. The Master delay hardmacro measures parts of the clock period using precise analog delay elements and provides a 90-degree delay over PVT. The READ and WRITE datapath hardmacros provide a data interface between the controller logic and memory. The datapath hardmacros support data transfers to and from the QDR-SRAM on both edges of the clock, effectively doubling the data throughput.

The QDR-2 core is built to support burst lengths of 2 and 4, programmable delay for read operation, write data phase alignment of 0 or 90 degrees to the output clock, and SCAN and BIST functions. The core uses a delay locked loop to maintain constant programmable delay over PVT. Routing within all hardmacros is optimized for operation up to 333MHz/667Mbps across all process, voltage and temperature conditions. LSI Logics special HSTL I/O driver and receiver are built to operate at either 1.8V or 1.5V allowing system designers to switch to future lower power devices. The HSTL I/O supports multiple impedance modes, driver impedance control, has excellent duty cycle matching and provides an electrical interface of superior signal integrity.

About CoreWare
The LSI Logic CoreWareIP library provides the industrys most comprehensive set of IP solutions that are proven and designed to work seamlessly with the standard-cell ASIC and RapidChipTMPlatform ASIC design flows. CoreWare IP includes GigaBlazeand HyperPHYhigh-speed standards-compliant SerDes, high-performance ARM and MIPS processors and associated systems, licensable ZSPDSP cores, processor peripherals and AMBA on-chip-bus structures, USB cores, Memory PHYs and Controllers, Ethernet MAC and PHY cores, PCI Express, XGXS, SPI4.2 and other protocol layer IP. Customers can leverage CoreWare IP solutions to significantly reduce risk and turn-around times with complex SoC designs. Additionally, a dedicated worldwide IP support organization is available to assist customers in all aspects of CoreWare SoC design.

About LSI Logic Corporation
LSI Logic Corporation (NYSE: LSI) is a leading designer and manufacturer of communications, consumer and storage semiconductors for applications that access, interconnect and store data, voice and video. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035, http://www.lsilogic.com.