The industry’s first device to combine FPGA flexibility and ASIC efficiency in a fully user programmable platform is being prepared for volume production
CUPERTINO, CALIFORNIA — June 29th, 2004 — Leopard Logic, Inc. today announced the successful qualification of the Gladiator CLD6400, the first member of the ground breaking Gladiator™ CLD™ family of user configurable logic devices. The only devices on the market to combine FPGA flexibility with ASIC efficiency, Gladiator CLDs provide significant performance, power and cost advantages over traditional FPGA and ASIC technologies by utilizing an innovative combination of patented field-programmable (FP) and mask-programmable (MP) fabrics.
As the first device of the family, Gladiator CLD6400 has been available for customer designs since spring, and has now successfully completed functional testing and qualification for important parameters, required for the correlation of the timing libraries to the actual silicon performance. This correlation enables users to accurately predict device performance based on the ToolBlox™ design tools and to achieve timing closure at their desktop within hours and without the need for lengthy and expensive design iterations needed for ASIC-like device architectures. The device exhibits unmatched performance with true system speeds of up to 500MHz and power dissipation of less than 6 watts.
The CLD6400 features 6.4M system gates and 2.3Mb of on-chip memory, which puts it on par with the largest FPGAs on the market but it provides 2-4x performance advantage at significantly reduced cost and power. With 32 GMAC/second DSP throughput, 16 on-chip PLLs and DLLs to drive global clocks and implement high-speed interfaces, the devices are ideally suited for high-speed applications. The design flow utilizes industry leading tools from Synopsys, Mentor Graphics, and Accelchip. Manufactured in TSMC’s 0.13 CMOS process on 300mm wafers, the Gladiator CLD6400 addresses the critical market need for user defined low risk platforms with fast development times and low unit and NRE costs.
The first several customer designs from technology leaders have successfully been mapped into the CLD6400 and are targeting networking, wireless and video applications. First production shipments to customers are scheduled for delivery for Q3, 2004.
“This qualification was a critical milestone towards delivering the Gladiator CLD6400 devices to our first customers. We are extremely pleased with the silicon results, as they demonstrate the superior performance of our architecture over other approaches,” said Chris Phillips, President and CEO of Leopard Logic. “We now have the solid basis in place to grow our business as we are moving ahead with the other devices on our product roadmap.”
The Gladiator CLD Family
The Gladiator CLD family of configurable logic devices features an innovative new architecture that combines ASIC and FPGA technologies into the industry’s first 100% user programmable implementation platform for system designers. Customers can perform instant design changes as with FPGAs, while leveraging the more efficient ASIC logic for the fixed blocks of their design. The result is a solution that defines a new standard for high performance, flexibility, low power, and fast turnaround time at the lowest total-cost-of-ownership for production volumes between 1,000 to 100,000 units.
Leopard Logic’s patented technology features the industry’s first fully hierarchical, directly buffered, point-to-point interconnect, which is at the root of Gladiator’s superior speed, utilization, predictability and reliability. The SRAM based HyperBlox FP fabric can be reprogrammed by the user anytime. The HyperBlox MP fabric uses the identical logic cell architecture, but replaces the SRAM configuration with a single-layer mask configuration to achieve significantly higher density, increased performance and lower power consumption. The HyperBlox FP and MP fabrics are combined with optimized memories, multiply-accumulate (MAC) units and flexible high-speed I/Os to realize a fully customer configured design. Leopard Logic’s unified ToolBlox™ design environment allows rapid timing closure at the designer’s desktop without tedious design iterations or exposure to back end, silicon deep sub-micron (DSM) issues.
About Leopard Logic, Inc.
Leopard Logic, a fabless semiconductor company headquartered in Cupertino, CA, has pioneered Gladiator CLD, a new class of configurable logic devices that combine FPGA and ASIC technologies in a 100% user programmable platform. The unique combination of Leopard Logic patented field-programmable and mask-programmable technology delivers unmatched performance and flexibility, short time-to-revenue and the lowest total-cost-of-ownership. Gladiator CLD devices can be used across a wide range of markets and applications requiring flexible logic solutions and are ideal for demanding applications in the networking, storage and digital consumer infrastructure markets. A comprehensive tool suite, first-class third party IP cores, and complete integration and design services complement the devices. For more information visit our website at www.leopardlogic.com
Leopard Logic and the Leopard Logic logo are registered trademarks of Leopard Logic, Inc. Gladiator, CLD, HyperBlox and ToolBlox are trademarks of Leopard Logic, Inc. All other trade names are the service marks, trademarks, or registered trademarks of their respective owners.