The patent was granted for innovative single-via customizable multi-layer routing fabric
San Jose, California, July 7, 2004 -- eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that it has received its tenth patent entitled “Customizable and programmable cell array” (6,756,811), issued on June 29, 2004 by the United States Patent and Trademark Office. This patent protects eASIC’s routing fabric that uses a single via for customization and applies to any metal routing fabric that comprises at least three metal layers. With this addition, eASIC’s patent portfolio broadly covers the company’s Structured ASIC fabric that features FPGA-like SRAM-LUT logic programmability combined with segmented standard metal routing, customized by a single via layer. This patented technology allows eASIC to offer a fast-turn Structured ASIC with no NRE (Non Recurring Engineering) cost, effectively using the maskless customization technique of Direct-Write eBeam.
The eASIC fabric presents a unique breed of Structured ASIC with an interconnect approach that eliminates all the pitfalls of FPGA. This technique employs only a single via layer (via-6) for routing customization, keeping all metal layers standardized and pre-fabricated up to metal-6. Through its reprogramming capability and efficient interchange between logic gates and memory bits, eASIC’s fabric features higher flexibility and ease-of-debug compared to other cell-based ASICs. And through its customized interconnection approach, eASIC provides significantly lower production unit cost and higher performance compared to FPGAs. This technology, called Structured eASIC, is the foundation for a set of product families that is being developed with strategic partners. eASIC’s goal is not to keep its technology as trade-secrets but rather to open it by joining forces with industry leaders in order to develop a complete solution, based on its breakthrough technology. Securing a comprehensive and broad patent portfolio, while sharing the product development with partners, epitomizes the company’s business strategy. eASIC’s unique business approach is aimed at making the Structure eASIC available to customers through multiple sources, reducing customer risk and providing broader ASIC offerings by leveraging each of their partners’ strengths.
“We are pleased with this additional recognition of eASIC’s breakthrough technology,” said Zvi Or-Bach, eASIC President and CEO. “Our patent portfolio includes broad and fundamental claims, providing eASIC with a strong IP protection. eASIC was founded based on identifying early on the need for a new ASIC design alternative now called Structured ASIC. eASIC’s technology is the only solution that can provide NRE-free ASIC together with low production unit cost and high performance. Our Structured eASIC technology constitutes a paradigm shift in ASIC, reinvigorating innovation in silicon by once again allowing affordable ASIC designs.”
eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. eASIC’s technology enables rapid and low-cost ASIC and System-on-Chip designs by its innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.
Headquartered in San-Jose California, eASIC Corporation is a privately held company, founded in 1999 by Zvi Or-Bach, the founder of Chip Express. Or-Bach is viewed by many as the “father of Structured ASIC technology”. www.eASIC.com
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