LONDON Jennic Ltd. (Sheffield, United Kingdom) has developed an intellectual property core for forward error correction (FEC), which it expects will become a key part of all 40-Gbit/second optical network systems due to the prevalence of low-quality signals in high-speed optical communications, particularly those that use dense wavelength division multiplexing (DWDM).
Jennic's FEC core can handle Reed-Solomon coding at speeds up to 44 Gbit/s when built on a standard 0.18-micron process. The company said it has started to port the core to a 0.13-micron process, which should cut its power consumption from 1.8 watt at 40 Gbit/s and lead to a smaller die size.
The company said its approach saves power over competing FEC approaches.
"We increased the latency of decoding, so that we can spread operations over a longer period of time," said Phil Chambers, who leads the FEC program at Jennic. "The latency is pretty acceptable. It is 500 clock cycles, but the FEC is dwarfed by the latency of framing and processing that gets performed in upper layers."
The company has designed the core to support the error correction schemes specified by the ITU Telecommunication (ITU-T) Sector's G.709 and G.975 standards, which are now being applied to 10-Gbit/s Ethernet and OC-192 systems.
The Jennic FEC core will form part of a complete engine with layers for framing, processing and interface.
"That is our next-generation optical networking product. It is a Layer 2 Sonet framer architecture," said Brian Bennett, marketing director for Jennic. "It is a superset of every possible combination of function. Customers select which way data comes in and how it goes out. The FEC came out of that digital wrapper work."
Because the G.709 'digital wrapper' standard is a stable draft but is not complete, Jennic has developed a bus that lets equipment suppliers manipulate the wrapper's bit formats, said Peter Wotton, systems architect for Jennic. "The first implementation we are doing will put overhead bytes on an 'overhead bus' so that you can handle those off-chip. Users can have that processing done on an FPGA" to ensure that the bytes are supplied in the right format without requiring a change to the mask for a chip carrying the core.
Jennic claims to be first supplier to offer a 40-Gbit/s FEC design on the open market, though a number of silicon suppliers are developing their own implementations based on work at the 10-Gbit/s level. As the distances for 10-Gbit/s communications grow longer, equipment builders have started to regard FEC as a necessity.
"We have people talking about long-haul and ultra long-haul communications. To do that, FEC is a necessity," said Gregg Borodaty, general manager of the telecom division of Vitesse Semiconductor Corp. "In the 10-Gbit/s space it is already prevalent. At 40 Gbit/s, it is becoming critical."
Giga A/S, an Intel company, has "started work on OC-768 [40 Gbit/s]," said Nikolaus Lange, managing director of Giga. "In 10 Gbit/s, FEC has become accepted as a standard."
Lange said that equipment suppliers are likely to start 40-Gbit system designs with the basic form of FEC, which adds 7 percent of overhead for a gain of around 6 dB, but will move to more advanced forms.
The optical amplifiers and muxes in DWDM "really reduce the quality of the signal," Lange said. "No one thought about FEC" at communication speeds up to 2.5 Gbits/s, he said. "But data transmission in the fiber is not ideal, and is definitely not ideal in DWDM. There can be pretty distorted optical channels and we need to hide this from the user.
"I believe there will be other FEC rates. A 25 percent overhead sounds pretty reasonable."
Noting "a lot of crosstalk issues with fiber when deploying 40 Gbits/s," Stuart Robinson, manager of strategic marketing of PMC-Sierra Inc.'s optical division, said the availability of DWDM and the problems with 40-Gbit/s communication has taken "the edge off the dem and."
Jennic is sticking with the basic Reed-Solomon 255,239 codes for its 40-Gbit/s core, but said it is looking at more advanced codes that will allow higher gains.
The company will support both in-band and out-of-band FEC, the latter being more commonly supported in the market at 10 Gbit/s. Agere Systems claims to be the market's only commercial supplier of in-band FEC. Agere recently launched a chip that caters to both in-band and out-of-band FEC.
Instead of demanding higher bit rates to carry payload and FEC information together, in-band FEC employs bytes in the Sonet header to 'transparently' add FEC without affecting physical layer interfaces, although in-band FEC offers lower gain than out-of-band protocols.
Vitesse's Borodaty said there are risks in employing unused in-band FEC overhead bytes. "They may be used for signalling," he said. "We have not been as active because the amount of gain it provides is not very large. The gain from out-of-band [FEC] is much more significant."
Chris Edwards is editor of Electronics Times, EE Times' sister publication in the United Kingdom.