Tower Semiconductor selects Virage Logic's Semiconductor IP for 0.13-micron offering

MIGDAL HAEMEK, Israel and FREMONT, Calif., July 20, 2004 — Tower Semiconductor (Nasdaq:TSEM; TASE:TSEM), a world-class independent wafer manufacturer, and Virage Logic Corporation (Nasdaq:VIRL), a leading provider of semiconductor intellectual property (IP) platforms, have signed a licensing agreement under which Virage Logic’s Technology-Optimized Platforms will be made available on Tower’s 0.13-micron CMOS processes.   

Under the terms of the agreement, Tower customers can access Virage Logic’s Technology-Optimized Platforms – comprising highly differentiated, silicon-proven embedded memories, standard cell logic libraries and I/O libraries – on Tower’s 0.13-micron TS13SL (standard logic) process, followed by support for its 0.13-micron TS13LP (low power) process.  In addition, Tower customers will have access to Virage Logic’s rich portfolio of highly differentiated IP including the Self-Test and Repair (STAR) Memory SystemTM and the patented Area, Speed and Power (ASAP) Logic™ Metal Programmable Cell Libraries. Because of the longstanding partnership between the two companies, Virage Logic was given early access to Tower’s process and significant elements of the Virage Logic Technology-Optimized Platforms are already silicon-proven on Tower’s 0.13-micron process. 

“We selected Virage Logic because of our mutual success in previous technology generations, silicon-proven libraries on our process and their commitment and focus on delivering highly differentiated IP,” noted Doron Simon, president, Tower USA Inc.  “As we introduce our 0.13-micron offering, it is critical that we work with a partner that has experience in advanced process technologies. Our growing worldwide customer base can now gain a competitive advantage in terms of cost and performance.”

“We are pleased to extend our successful partnership with Tower to include support of Tower’s most advanced technologies in its world-class fab with our Technology-Optimized Platforms,” said Adam Kablanian, president and chief executive officer of Virage Logic.  “In addition, with access to the STAR Memory System, which substantially reduces test costs and improves overall yield, and our patented ASAP Logic Metal Programmable libraries, which save configuration costs by reprogramming only a few masks, Tower’s customers can realize significant savings and achieve a shorter time-to-volume.”

About Virage Logic’s Technology-Optimized Platforms

Building on its differentiated technology and market leadership position, Virage Logic’s Technology-Optimized Platforms, which are custom-tuned to a target manufacturing process,   aim to meet the critical requirements of reducing design time, silicon area and design risk, while boosting performance and enhancing manufacturing yields.  By providing silicon-proven, fully characterized IP that is tuned to all major electronic design automation (EDA) design tools and flows, Virage Logic’s Technology-Optimized Platforms address the needs of complex and mainstream System-on-Chip (SoC) designs.

Virage Logic’s Technology-Optimized Platforms are based on the ASAP MemoryTM High-Density (HD) memories, the ASAP Logic HD Standard Cell libraries, and the company’s Base I/O libraries.  Technology-Optimized Platforms help customers expedite the creation of next-generation SoCs by providing silicon-proven IP optimized for a targeted technology node and process.  Technology-Optimized Platform users have optional access to Virage Logic’s rich portfolio of highly differentiated IP including the STAR Memory System, the patented ASAP Logic HD and HS Metal Programmable Cell Libraries, and access to specialty I/Os such as SSTL, HSTL, PCI, PCI-X, and USB1.1. 

Availability

Front-end views for Virage Logic’s Technology-Optimized Platforms for Tower’s 0.13-micron process are expected to be available by Q3 2004.

About Tower Semiconductor Ltd.

Tower Semiconductor LTD. is a pure-play independent wafer foundry established in 1993.  The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13 micron; it also provides complementary technical services and design support.  In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies.  To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 micron and can produce up to 16,000 150mm wafers per month.  Fab 2 features 0.18-micron and below process technologies, including foundry-standard technology.  When complete, Fab 2 is expected to offer full production capacity of 33,000 200mm wafers per month.  The Tower Web site is located at www.towersemi.com.

About Virage Logic

Founded in 1996, Virage Logic Corporation (Nasdaq:VIRL) quickly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Virage Logic has evolved to become a global leader in semiconductor IP platforms comprising embedded memory, standard cells, and I/Os primarily for the consumer, communications and networking, handheld and portable, and computer and graphics markets. Virage Logic’s highly differentiated product portfolio provides foundries, integrated device manufacturers (IDMs) and fabless customers with key competitive advantages including higher performance, lower power, higher density and optimal yield. The company’s comprehensive quality efforts are validated in its FirstPass Silicon Characterization lab which ensures high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.

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SAFE HARBOR STATEMENT FOR TOWER SEMICONDUCTOR LTD

This press release includes forward-looking statements, which are subject to risks and uncertainties.  Actual results may vary from those projected or implied by such forward-looking statements.  Potential risks and uncertainties include, without limitation, risks and uncertainties associated with: (i) the successful completion of the 0.13 micron process technology transfer (ii) market demand for 0.13 micron technology manufacturing services; (iii) final qualification of the 0.13 micron process (iv) timely and successful validation of 0.13 micron IP offering; A more complete discussion of risks and uncertainties that may affect the accuracy of forward-looking statements included in this press release or which may otherwise affect our business is included under the heading “Risk Factors” in our most recent Annual Report on Form 20-F and in our Form F-3, as amended, as were filed with the Securities and Exchange Commission and the Israel Securities Authority.

SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:

Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships.  Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements.  These risks and uncertainties include Virage Logic’s ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic’s ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic’s ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic’s technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company’s ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company’s ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company’s Annual Report on Form 10-K for the period ended September 30, 2003, and in Virage Logic’s other periodic reports filed with the SEC, all of which are available from Virage Logic’s website (www.viragelogic.com) or from the SEC’s website (www.sec.gov), and in news releases and other communications.  Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release. 

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