Intellectual Property Support for LatticeECP, LatticeEC FPGAs Announced by Lattice Semiconductor, Digital Core Design

IP cores enable customers to quickly implement a wide variety of functions in Lattice programmable logic devices

HILLSBORO, OR, USA / BYTOM, POLAND - August 2, 2004 - Lattice Semiconductor Corporation (NASDAQ: LSCC) and its IP partner, Digital Core Design (DCD), today announced intellectual property (IP) support for the new LatticeECP-DSP^TM ("EConomyPlusDSP") and LatticeEC^TM ("EConomy") FPGA device families. Through the ispLeverCORE^TM Connection program, Lattice and Digital Core Design will provide a range of complete system solutions for their mutual customers who are integrating system-level IP with the most advanced silicon architectures. The Lattice partners program is designed to allow customers to easily access and integrate approved third-party IP products using Lattice programmable devices.

"Lattice is pleased to continue our partnership with Digital Core Design, an IP company with an extensive portfolio that specializes in improved architectures for MPU/MCUs, floating point unit (FPU) co-processors, and peripherals," said Stan Kopec, Lattice vice president of corporate marketing. "DCD is also committed to providing total customer solutions, evidenced by the debugging software and hardware they've developed for their 8051 and 80390 processor cores. We're very excited by the increased IP core performance that Digital Core Design has achieved using our new ispLEVER® software," Kopec concluded.

Tomek Krzyzak, VCEO of Digital Core Design said, "Our experience using the new ispLEVER software has been very good; without question, the tools compare favorably to other leading FPGA vendors' tools. The new LatticeECP^TM and LatticeEC devices are much faster than previous FPGAs, and our customers will also appreciate the low-cost, feature-rich capabilities of these new products."

LatticeECP & LatticeEC Cores from Digital Core Design
Digital Core Design has ported, optimized and tested a selection of their flagship IP cores on the new Lattice FPGA devices. The initial IP cores from Digital Core Design that support the new devices, and their increased performance compared to other Lattice FPGA devices, are shown on the Lattice website: www.latticesemi.com/products/devtools/ip/dcd/index.cfm

Digital Core Design Sample IP Core Performance on Lattice FPGAs
Digital Core Design Product	ORCA®4	LatticeEC	Improvement
DI2CM: I2C Master	69 MHz	226 MHz	+328%
DI2CS: I2C Slave	97 MHz	228 MHz	+235%
DI2CSB: I2C Slave Base	129 MHz	231 MHz	+179%
DSPI: Serial Peripheral Interface - Master/Slave	121 MHz	204 MHz	+169%
DFPIC165X: 8-bit RISC MCU	54 MHz	64 MHz	+119%

These Connection Cores are available in netlist format for immediate purchase from Digital Core Design. Digital Core Design also offers a variety of additional packaging and licensing options to suit specific customer needs. By leveraging partner products, customers can quickly implement a wide variety of functions in Lattice programmable devices.

About the LatticeECP-DSP and LatticeEC FPGA Families
Introduced June 28, 2004, the LatticeECP-DSP and LatticeEC FPGA device families are architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace.

About Digital Core Design
Digital Core Design (DCD), a privately held company founded in 1999, is a charter member of the Lattice ispLeverCORE Connection program and is a leading intellectual property provider for PLD and ASIC designers. The company provides high-quality, low-cost synthesizable IP cores in VHDL and Verilog for components such as microcontrollers, bus interfaces, arithmetic co-processors and other arithmetic components. Designed from the ground up to meet SOC requirements, DCD's products offer:

• An industry-leading combination of high performance, low power, and small die size
• Easy system integration with peripherals, co-processors, and memories
• Easy customization for adaptability to a wide range of applications
• A choice of robust third party development and software tools
• An ASIC-style implementation methodology that leverages commercially available design tools

Specializing in modifications of existing popular microcontrollers and microprocessors, Digital Core Design offers new and improved microcontroller architectures that are 100% software compatible with their predecessors. The processors can be integrated with a broad range of available peripherals, including Timers, UARTs, I²C interface, SPI interface, Compare/Capture, Watchdog Timer and fixed/floating point co-processors.

Digital Core Design also specializes in the development of unique Fixed and Floating Point arithmetic co-processors, and IEEE 754 compliant pipelined floating point units, which allow for extremely fast floating point computation. Digital Core Design is located in Bytom, Poland, and sells its products through a worldwide network of distributors. Company headquarters are located at Wroclawska 94, 41-902 Bytom, POLAND; Telephone +48 32 282 82 66; FAX +48 32 282 74 37. For more information about Digital Core Design, visit their World Wide Web site http://www.dcd.pl/

About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP™ Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC™), and Programmable Digital Interconnect (GDX™). Lattice also offers industry leading SERDES products. Lattice is “Bringing the Best Together” with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer and intellectual property suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ISP, LatticeEC, LatticeECP, LatticeECP-DSP, ispLEVER, ispLeverCORE, ORCA, GDX, PAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. .

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.