3Plus1 Technology emerges from stealth mode; Heterogeneous Multiprocessor architecture creates low-power, high-performance CoolProcessor family
SARATOGA, California—August 2, 2004 — 3Plus1 Technology Inc., a Silicon Valley-based fabless semiconductor company, today announced details of the company and an advanced multiprocessor architecture conceived from the ground up to run next-generation handheld systems. The architecture has been used as the basis for a series of CoolProcessor™ devices aimed at addressing the low-power needs of mobile-system manufacturers.
Formed over a year ago, 3Plus1 has been developing a processor family aimed at solving the problems highlighted by Yrjo Neuvo, Nokia SVP and Senior Technology Advisor. In his plenary address at ISSCC this year, Neuvo stated that the need for processing simultaneous multimedia and communications applications are leading to excessive power dissipation and to increasing costs of next-generation mobile systems. This view is echoed by many mobile-system OEMs. Faced with today’s solutions, which dissipate around 3000mW, next-generation mobile handsets combining additional voice, video and data applications need to have a power budget of no more than 2000mW, given realistic battery capacities, according to Neuvo.
3Plus1 Technology has created an architecture specifically designed for low-power, concurrent execution of specific applications, including MPEG 2/4, H.263/4, JPEG/2000, 802.11 a/b/g, 802.16 Bluetooth, GSM/GPRS/EDGE, CDMA 2000/WCDMA, MP3, and GPS, in various combinations. This has been accomplished in a sub-100mw processor when implemented in a standard 130nm low-power CMOS process.
“3Plus1 has taken Nokia’s challenge to the industry very seriously and is now delivering the first tools to leading OEMs that can result in products that meet Dr. Neuvo’s targets in 2005,” said Allan Cox, President and CEO of 3Plus1 Technology.
“One of the largest opportunities in the semiconductor industry is the supply of low-power processors that can support high-volume application systems, such as, smart phones, wireless enabled cameras and mobile PCs,” stated Dr. Handel Jones, President of International Business Strategies Inc. “The conventional architectural approaches, such as RISC, CISC, etc., that rely on traditional scaling to 90nm, 65nm and below, are facing increasingly difficult challenges in controlling power, cost, performance and time-to-market.” Jones added, “The approach of operating the architecture at higher performance levels is not effective. 3Plus1 has a very interesting and promising technology that is a candidate to support high-volume applications found in the multi-function wireless market.”
Self-financed by its founders since its inception, the company is addressing the needs of the 600-million-plus mobile handset, camera and PDA market. 3Plus1 has assembled a group of world-class technologists, including leading academics in their fields, addressing the problems of real-time voice, video and data processing—at ultra low power levels and minimum silicon die size—from the fundamental software and hardware architectural perspectives.
“Architectural solutions that exploit the heterogeneous concurrency of the applications are, in the long run, the only viable solution,” stated Jan Rabaey, Professor at UC Berkeley and Director of the Berkeley Wireless Research Center (BWRC) and the MARCO Gigascale System Research Center (GSRC). Rabaey, a technical advisor to 3Plus1, added, “Previous attempts to create such architectures have mostly failed for a variety of reasons, most importantly the lack of a smooth integration between the hardware and software layers, as well as the clear match between the applications and the hardware computational modules. The solution offered by 3Plus1 manages to address all these concerns in an elegant and versatile fashion. The CoolProcessor approach is superior to anything I am familiar with in terms of power and area efficiency, while providing great flexi bility and performance at the same time.”
Working with established leaders in the industry, 3Plus1 has created links to leading companies in the area of RISC processors, system simulation, application software and SoC integration. The company has joined the ARM Connected Community, aligned to provide a complete solution from design to manufacture and end-use for products using ARM technology. The company is working with CoWare Inc., a leader in system-level simulation, to demonstrate the CoolProcessor in the CoWare simulation environment as an integral part of the modeling solution. Having recognized customers’ needs for proven applications expertise, 3Plus1 has also been working with Hellosoft Inc., a leader in communications application software, in preparation for deployment of its first silicon. Finally, the company is taking advantage of the SoC integration capabilities pioneered by Sonics Inc. for rapid implementation of complex and demanding IP.
The CoolProcessor technology has been developed in record time, based on an internally developed, automated methodology, capable of generating RTL, simulation, analysis and verification tools automatically from a high-level relational database. “The development of a highly optimized programmable processor for a target set of applications demands continuous adjustment of tools and hardware design, even late into the development cycle, based on feedback from the application programming results,” said Dr. Amir Zarkesh, Executive Vice president of Engineering. “The very advanced nature of the CoolProcessor architecture has enabled the design and use of an automated methodology which is now working with excellent results.”
The CoolProcessor family comprises six members, all upwardly code compatible with a single programming model. Development of software applications follows a standard DSP tool flow and the company is currently delivering its initial applications-development software and modeling tools to early evaluation partners. The first member of the CoolProcessor family, the 3P3200, is capable of running combinations of MPEG, JPEG, GSM and 802.11 concurrently and is planned for release in Q2, priced at $8 in quantities of 10K pieces.
More information at: www.3p1t.com
Search Silicon IP
- SiCortex Inc. Licenses MIPS64 Architecture for Low-power, High-performance Teraflop Computing
- NEC Electronics America Uses Cadence Encounter for High-performance, Low-power ARM11 Processor
- Fujitsu Develops Technology for Low-Power, High-Performance 45nm Logic Chips
- ARM Selected To Deliver Low-Power and High-Performance Libraries For IBM, Chartered and Samsung 45-Nanometer Common Platform Technology
- Toshiba Microelectronics Selects ARM OptimoDE Technology For High-Performance, Low-Power Data Engines
- Green Hills Software adds support for production-ready RTOS and tools to Imagination Technologies' RISC-V CPUs
- Kalray Announces Production Launch of New "Coolidge™2" DPU Processor Optimized for AI and Intensive Data Processing
- Global Semiconductor Sales Increase 0.3% Month-to-Month in April
- Defacto will celebrate its 20th anniversary at DAC with customer presentations and major technical announcements
- VeriSilicon Obtained Bluetooth 5.3 Certification for Its Complete Bluetooth Low Energy Solution
- GlobalFoundries and STMicroelectronics Finalize Agreement for New 300mm Semiconductor Manufacturing Facility in France
- Are Chiplets Enough to Save Moore's Law?
- Nanusens announces that it can now create ASICs with embedded sensors
- Consortium's Move Will Boost RISC-V Ecosystem, Thankfully
- Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe
|E-mail This Article||Printer-Friendly Page|