Company's x1 PCI-Express PHY Leads Industry With Smallest PIPE Core Area
SAN FRANCISCO, CA - AUGUST 30, 2004 -- TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, will be exhibiting at this year's Intel Developer FORUM 2004. The event is sponsored by Intel Corporation and is being held September 7-9, 2004 at Moscone South, in San Francisco, California. TriCN will be exhibiting in the PCI-Express Community, booth # 1139. TriCN CTO Ron Nikel will be speaking at the Intel Developer FORUM in San Francisco on Sept. 8th at 5:15 pm [http://www.tricn.com/IntelDevForum2004.html]
In June 2004, TriCN introduced its PCI Express PHY product family that supports all lane configurations, including x1, x2, x4, x8, x12, x16 and x32. These PCI Express PHYs incorporate TriCN's proprietary TriDL!" digital SerDes technology, providing significant area and power advantages over competing analog solutions. What differentiates TriCN's PCI Express x1 lane configuration is its true single lane design. This is a departure from many competing offerings that simply disable multi-lane PHYs, penalizing customers with unnecessary area overhead. The result is a x1 design requiring only .68 sqmm, nearly 40% smaller than the nearest competitor.
TriCN's PCI Express PHY products are immediately available in the TSMC 130nm process. All are PCI Express 1.0 and PIPE 1.0a compliant, and include the SerDes, the PIPE logic and the I/Os. The products are delivered as a hard macro requiring no further RTL synthesis, significantly reducing engineering time and risk over comparable solutions with soft IP components. The TriCN PCI Express PHYs support hot swap, lane reversal, per-lane at-speed internal loop back BIST, and both 250MHz/8 bit per lane and 125 MHz/16 bit per lane native interfaces.
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. All products are designed using rigorous signal integrity and timing analysis to ensure first time power-up success. Products include Base I/O libraries for pad-ring creation, high-performance memory and networking interfaces, multi-function I/O's compatible with multiple interface protocols, and multi-gigabit PHY products. TriCN's customers range from fabless semiconductor to systems companies and IDMs.
For more information, please visit TriCN's web site at www.tricn.com.