Consumer electronics now drives custom silicon technology and it demands efficient hardware differentiation and related solutions. These requirements include 5 million to 10 million gate systems that run faster than 250 MHz and support interoperability among multiple standards.
Solutions that match the demands of the consumer market are starting to appear. Custom systems-on-chip (SoCs) that incorporate large amounts of digital and mixed-signal intellectual property (IP) have superceded traditional gate-array-type ASICs. FPGAs are important for prototyping but inherently don't meet the consumer electronics market's requirement for high-volume silicon. Structured arrays, also known as structured ASICs, sit between FPGAs and custom SoCs. They offer low nonrecurring engineering costs but their fixed master slices render them uncompetitive except for low-volume markets.
Soft IP platforms, a relatively new custom SoC methodology that uses standard, presilicon proven IP and an efficient network interconnect system, shortens development time and minimizes timing closure problems. A hardware/software co-development environment allows customers to start developing their application software soon after the project starts without waiting for first silicon. Manufacturability, the ability to ramp highly complex chips to production volumes quickly, is essential.
Custom SoCs for consumer electronics applications must incorporate preproven, reusable digital IP. For example, today's intelligent cell phones are complex systems. A high-end cell phone may incorporate ports for 802.11, Bluetooth, IrDA, GPS and USB; a digital camera with one megapixel or more of resolution; databases for address books or calendars; and color graphics display capability for Internet viewing. They often require three processing engines on a single SoC: one for the communications functions, one for the applications software and a digital signal processor to handle the data processing. The design may contain 20 to 30 or more digital IP blocks, the microprocessor cores and multiple mixed-signal IP blocks. Verifying, testing and finishing the system on schedule is a major challenge.
Multiple standards support
A daunting number of standards must be supported by consumer electronics products, even for simple products like cell phones or DVD recorders. DVD recorders, for instance, have about eight audio compression formats, multiple video compression standards and an assortment of digital rights management (DRM) standards. Most of these standards are handled by the application software, increasing the software content and processing requirements of a system chip. In addition, much of this data processing has to be in real-time, which is one of the factors pushing up embedded microprocessor and clock rates above 250 MHz.
Since the real world is analog, most custom SoCs incorporate multiple digital-to-analog converters (D/As) and/or analog-to-digital converters (A/Ds.) Neither a fixed master slice technology such as structured arrays nor FPGAs accommodates the number of instances efficiently. Even a simple A/D requires a high degree of optimization. Resolution requirements can be anywhere from 6 to 16 bits. Moreover, chip designers must minimize crosstalk and noise. In addition, device package and printed-circuit board characteristics must be taken into account. Production test also needs to be considered so that the parts can be tested cost-effectively without using expensive test systems on the production floor. This is usually solved by a combination of loop-back tests and built-in self-test.
Short market windows
All these challenges must be compressed into a short design cycle with parallel development of the hardware and the application software and with methodology to ensure first-time success. The designer's reusability strategy must be used in conjunction with an IP integration scheme that allows early creation of an emulation system that supports co-software development.
The Soft IP Platform systemized approach enables interconnecting of the many different IP blocks on a network or backplane in a shorter time than traditional design practices. The designer has to ensure that all the IP blocks have the necessary bandwidth and latency to meet performance targets. For this designers often use prewrapped Open Core Protocol blocks and stitch them together with a Sonics interconnect network backplane.
Once the complete RTL for the design is available then many activities can start in parallel. Designers can spend time verifying the system at a functional level rather than working to debug the block interconnects where historically most of the bugs tended to be.
For example, at the functional level designers can look for any system-level problems such as confirming that the NAND flash controller works with all the new NAND flash architectures on the market. If they find a problem, they can fix the controller source code and easily reintegrate it into the system. The backend physical designers can work on the first trial chip layout to confirm that the design is within its size, performance and power budgets. While the RTL is being verified, it can also be ported to the hardware/software co-simulation environment to allow verification of the application software code.
With the traditional ASIC methodology, this is a task that often had to wait until the team had gotten back working silicon chips.
Frank R. Ramsay (email@example.com) is director of strategic marketing in the ASIC and Foundry Business Unit of Toshiba America Electronic Components, Inc. (San Jose, Calif.)
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