As process technology evolves to the submicron level, traditional IC design houses are facing tremendous challenges in higher mask charge and longer production cycle. For example, in the case of a 90 nm mask, the cost can be as high as 1.5 million US dollars and the wafer production time (inclusive of testing) is now around 180 days. Coupled with two other factors inherent in advanced SoC design, that is, startling IP cost and prolonged development time, smaller IC design houses retain even less chance of measurable profits. Some may resort to FPGA as an alternative, but then the high unit cost, low speed, lack of analog cells, and high power consumption emerge as another stumbling block. In light of these, Faraday now comes up with an effective solution: TEMPLATETM.
TEMPLATETM realizes a new breed of design concept. It is a hardware-based platform with pre-defined logic and analog IPs, embedded memories, RAMs and I/Os. By capitalizing on the Metal Programmable Cell Array (MPCA) technology, the designer need only modify the top three metal layers to churn out the desired designs while still meeting the programmability of the FPGA. Let us examine how far and well TEMPLATETM can shorten the design cycle and lower the cost. First and foremost, a large portion of the initial mask charge and staged wafer cost is absorbed by Faraday; the designer needs only to assume the mask charge of the top three metal layers (which is less than 1/10 of the overall mask charge). Besides, since it is only necessary for the designer to make changes to and wait for completion of manufacture of the top three metal layers, the overall design cycle can be reduced drastically (1/10 of the original). Meanwhile, in combination with Faraday¡¯s complete portfolio of silicon proven IPs, TEMPLATETM delivers excellent signal integrity, high chip yield, and hence premium overall quality, that contribute further to minimizing the risks typically associated with advanced SoC design and maximizing design wins.
Faraday¡¯s 0.13 µm TEMPLATETM Family (Table 1) is designed according to UMC¡¯s standard logic process, and since TEMPLATETM Family adopts traditional ASIC design flow clients can simply use design flow they are familiar with without purchasing any new EDA tools. With Faraday¡¯s rich experience in ASIC design service, the TEMPLATETM clients can enjoy satisfactory design service including timing closure, verification, testing, and sampling fabrication within 10 to 12 weeks!
Table 1: 0.13 µm TEMPLATETM Family
| TEMPLATE | FIT9200 | FIT9300 | FIT9400 | FIT9500 | FIT9600 | FIT9700 | FIT9800 |
| Usable ASIC Gates | 256K | 1024K | 1024K | 2366K | 2048K | 4352K | 6400K |
| Total RAM bits | 512K | 1024K | 768K | 1536K | 1664K | 2560K | 4224K |
| Number of PLL | 4 | 4 | 4 | 4 | 6 | 8 | 12 |
| Number of DLL | 0 | 2 | 2 | 2 | 2 | 4 | 4 |
| 32-bit CPU | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| USB OTG | 0 | 0 | 1 | 1 | 2 | 2 | 2 |
| E'net 10/100 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
| OSC/POR/VDT | ¡¦ | ¡¦ | ¡¦ | ¡¦ | ¡¦ | ¡¦ | ¡¦ |
| System clock Speed | 600MHz+ | 600MHz+ | 600MHz+ | 600MHz+ | 600MHz+ | 600MHz+ | 600MHz+ |
| Max. IO available | 208 | 292 | 292 | 388 | 484 | 484 | 580 |
About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, USB 2.0, Ethernet, PCI-Express, and Serial ATA. With more than 500 employees and 2003 revenue of $111 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other markets, world-wide. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: http://www.faraday-tech.com