In order to achieve the productivity necessary to complete an SOC, designers have been successfully turning to design reuse. SOC designers have relied on intellectual property (IP) vendors for "implementation IP," pre-designed synthesizable or process-hardened chip functions. The most popular IP functions continue to be processors (e.g., ARM, MIPS and PowerPC) and standards-based on-chip and off-chip communications protocols (e.g., AMBA bus, PCI Express, USB 2.0 Host).
Since verifying an SOC requires more than half of the design budget and time, designers have also been using verification IP (VIP) blocks, especially for standard protocols. Designers use VIP just like IP, to increase productivity, save money and reduce risk, which is the EDA mantra.