SANTA CLARA, Calif. Innovations in platform design will be driven by FPGA vendors and their growing number of HDL-savvy FPGA designers, not ASIC vendors and designers, according to a keynote delivered at the HDL Conference by Mentor Graphics chairman and chief executive Wally Rhines.
Rhines said to an audience of approximately 200 that he believes FPGA vendors are in a great position to step to the forefront of platform-based design because they have a growing user base, because cost differences between volume FPGAs and ASICs are shrinking, and because their ability to support only limited products and platforms means design efforts will be more focused and innovations driven by their large user base will occur rapidly.
The number of HDL-savvy designers is expected to reach 200,000 by 2010, according to a graph Rhines displayed during his speech. He also showed a graph from Collett International displaying the rapid rise of HDL use in FP GAs. According to this graph, Verilog and VHDL were not used in 1995 by FPGA designers, but in 1997 they began to make an impact. "Today, 60 percent of FPGA designers are using VHDL, and roughly 16 percent are using Verilog," said Rhines. "When you enable more innovators you enable more innovation."
Rhines holds that the rise in HDL use in FPGA design over the last five years is an indicator that FPGAs' larger user base will mature FPGA technology at a faster pace than ASICs and thus platform as well as tool innovations supporting these platforms will occur rapidly.
"Whereas it took more than a 10-year period to put all tools in place for the typical ASIC design flow, most of these same tools are being introduced or are available for FPGAs today," he said. "What if FPGAs become the leading-edge platform around which we design tools, and ASICs become the follower?"
FPGAs have several advantages over ASICs, Rhines pointed out, including giving the user more control over the complete design and l ayout, quicker design cycle time, easier verification and no photomask costs.
Rhines concedes that ASIC will always provide users with higher usable gate density per unit area and better performance than flexible FPGAs. "But as that fixed cost burden moves up, then the unit volume moves out, so we get to the point where for a large share of any reasonable volume it is not unlikely that an FPGA will be just as cost-effective as an ASIC," said Rhines. "That is if you can achieve the same capability and performance."
Rhines noted that FPGA and ASIC companies are converging on reconfigurable architectures. ASIC vendors are creating ASICs with programmable cores and FPGA vendors are creating programmable-logic devices that include standard cell MPUs and DSPs. He predicts that FPGA companies will eventually take over this application-specific platform market.
"FPGA companies have to make more restrictive decisions than ASIC companies," said Rhines. "They have to pick only a single core or a couple of c ores in order to field the kind of support required to support an FPGA and the design around it. They will make choices that limit the alternatives. Then we throw in the 100,000 or 200,000 designers you can attract, and all of sudden you have a large group of designers innovating around a fixed set of restrictive functions. I think they will drive the next step in innovation."
Rhines predicts this will drastically change the EDA tools market.
"EDA vendors need a business model tuned to the low -cost, high-volume market," Rhines said. "EDA companies will need to have good-quality software that doesn't require large amounts of maintenance. We will need a different level of quality for tools than what we can put up with today. They have to be bullet-proof and self-supporting. We also have to have broad geographic coverage for these large numbers of designers. Indirect sales will be a must."