Retargetable System Verification Environment delivers transaction-based support for the SystemC Verification Library (SCV).
Woburn, Mass. — Nov. 16th, 2004 — Zaiq Technologies, Inc., a leading provider of complete design engineering solutions, today announced it is shipping version 4.3 of its Pre-configured Reusable Environment and testing Platform (PREP™). PREP provides chip and system designers with a pre-configured verification environment for electronic designs, along with a methodology to comprehensively and efficiently verify those designs. In addition to support for the SystemC Verification Library (SCV), performance enhancements to the library of verification IP and GUI improvements have now been added to the production release of PREP.
"Over the last several years verification teams have had increasing needs for the capabilities of constraint based randomization and advanced verification constructs in an open test language. Extending PREP to support the SystemC language and the open-source SystemC Verification Library, SCV 1.0 provides our customers with advanced features like constraint based test randomization, smart pointers, and transaction recording. Adding SCV support provides a natural evolution from C-based verification environments to the powerful new features of SystemC." said Rich McAndrew, Zaiq's Executive Vice President of SYSTEMware Products and Services. "We are proud to be in production with the next of several steps supporting SystemC. Adding these features, while maintaining an easy to use open language based verification environment which seamlessly supports simulation, hardware acceleration and emulation are key capabilities for true Electronic System Level verification."
As part of Zaiq Technologies SYSTEMware family, PREP allows rapid deployment of multi-language DV environments for projects with an initial pre-configured environment. PREP provides SCV 1.0 based templates and examples that allow users to quickly incorporate constrained randomized testing with no adverse effects on performance in either simulation, hardware acceleration or emulation. PREP's open standards verification environment supports unit, chip and system-level testing and facilitates verification IP reuse and provides powerful, reusable support libraries. PREP supports Verilog, VHDL, C/C++ and SystemC standard usage and tools, and interfaces with languages like Vera, System Verilog, and e.
About Zaiq Technologies, Inc. Zaiq Technologies, Inc. enables its customers to meet critical product development objectives by offering a complete line of specialized design and verification products and services. Zaiq is a recognized leader in system level design and verification for complex, high-performance, system-on-chip (SoC), ASIC and FPGA based systems. The Company's innovative domain-specific design methodologies enable the creation and integration of reusable IP. As a result, customers are able to achieve breakthroughs in the time-to-market and time-to-revenue delivery of complex systems. Zaiq Technologies was founded in 1996 and has completed well over 400 assignments.
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