Pipelined Intellectual Property Core Validated In-System At 200MHz/400DDR; Designed For High-Speed Operation Using Embedded DDR Support In LatticeECP/LatticeEC FPGA Devices
HILLSBORO, OR - NOVEMBER 22, 2004 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of a new ispLeverCORETM IP module, the DDR SDRAM Controller for the LatticeECPTM and LatticeECTM FPGA device families, with speeds validated in-system at 200MHz/400DDR. By comparison, the fastest speed claimed for similar IP in competitive low-cost FPGAs is 133MHz/266DDR.
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. Timing parameters that control specific DDR memory devices can be adjusted by the user through signals that are input to the IP module. In addition, the cores have been tailored to utilized dedicated hardware contained within the LatticeECP/EC devices that facilitate the implementation of high-speed DDR memory interfaces.
"The LatticeECP-DSPTM and LatticeEC FPGAs feature pre-engineered DDR memory interfaces, allowing them to achieve 400Mbps performance -- the only low-cost FPGAs to achieve this performance level," said Stan Kopec, Lattice vice president of corporate marketing. "This new memory controller IP core has been specifically designed to take advantage of that embedded DDR support, delivering high-speed operation in a low-cost fabric. As with all our ispLeverCORE IP, this module has been extensively tested, well documented and is supported by Lattice field and factory application engineers. This release further expands IP support for our LatticeECP and LatticeEC devices. Customers can take advantage of these new cores now to simplify their complex design efforts and speed their time to market," Kopec concluded.
Features of the DDR SDRAM Controller for LatticeECP/EC FPGAs
- Interfaces to industry standard DDR SDRAM
- High-Performance DDR 400/333/266/133 operation
- Programmable burst lengths of 2, 4 or 8
- Programmable CAS latency of 2 or 3 cycles
- Intelligent bank management to minimize ACTIVE commands
- Supports all standard DDR commands
- Synchronous implementation for reliable operation
- Command pipeline to maximize throughput
- Up to 8 chip selects for multiple DIMM support
- Supports all common memory configurations
- SDRAM data path widths of 8, 16, 32, 64 and 72 bits
- Variable address widths for different memory devices
- Programmable timing parameters
- Byte level writing through Data Mask signals
- Chip selects of 1, 2, 4 or 8 bits
- Burst termination
Availability and Pricing
The DDR Controller IP module is available now. List price is $4,000 for the netlist version with a single-project license with standard license terms. The Data Sheet and User's Guide for the DDR Controller IP core can be found on the Lattice website at http://www.latticesemi.com/ip
A free Evaluation Package also is available for immediate download on the Lattice website. Each IP Evaluation Pack contains a model for functional simulation and an evaluation netlist for fitting purposes and static timing analysis.
About Lattice ispLeverCORE IP
Lattice ispLeverCORE IP products are highly integrated, modular design blocks that can be reused and easily placed within a programmable logic design. The ispLeverCORE modules implement popular industry-standard functions, commonly known as intellectual property (IP) cores.
Lattice offers a growing line of ispLeverCORE modules, optimized for use with its device families. The ispLeverCORE modules are designed using the highest coding standards, and are extensively tested to meet required functionality and performance. These cores are ready-to-use, well documented, and are supported by Lattice field and factory application engineers. Most ispLeverCORE modules are designed to be parameterizable; i.e., the core can quickly be reconfigured to meet specific system needs.
About the LatticeECP and LatticeEC FPGA Families
The LatticeECP-DSP and LatticeEC FPGA device families are architected to provide the most optimized feature sets combined with the lowest total solution costs of any FPGAs. The new LatticeECP-DSP products, targeted for high-performance DSP applications, provide up to a 50% performance and 75% logic utilization improvement over other low-cost solutions when implementing common DSP functions. The LatticeEC FPGA product family, targeted for general-purpose FPGA applications, is a precise and targeted response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace.
About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP™ Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC™), and Programmable Digital Interconnect (GDX™). Lattice also offers industry leading SERDES products. Lattice is “Bringing the Best Together” with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, http://www.latticesemi.com.
Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.
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Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeEC, LatticeECP, LatticeECP-DSP, GDX, ISP, ispLeverCORE, PAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.