Multicore designs might force Intel off its bus; Integrated memory controllers may loom large in future designs
Multicore designs might force Intel off its bus; Integrated memory controllers may loom large in future designs
By Tom Krazit, IDG News Service
December 16, 2004
As Intel moves in step with the rest of the chip industry toward the multicore design era, it is preparing to overhaul the memory bus architecture that has served it well for so many years, according to company executives and analysts.
Multicore processor designs are considered the solution to the performance scaling problem brought on by increased amounts of power leakage in modern chips. Transistors are now so small that increasing a chip's frequency, and therefore the amount of power it consumes, is not the simple exercise that kept companies like Intel going for many years.
However, in order to fully realize the performance gains provided by multiple processor cores, chip companies need to find a way to deliver enough data to the processor from the main memory to keep those cores as productive as possible.
Intel's current front-side system bus design should be able to keep as many as four cores satisfied, depending on the frequency of those cores, said Stephen Pawlowski, an Intel senior fellow, at a recent briefing on Intel's multicore strategy
Related News
- Broadcom lays off 1,100; may lay off more
- Intel Unveils Industry's First FPGA Integrated with High Bandwidth Memory Built for Acceleration
- MoSys and Open-Silicon Pound Tharas Systems Design Into Production; Tharas Systems Hammer(R) Verification Appliances Powered by Large Number of High-Speed 1T-SRAM Memory
- Rambus to Demonstrate the World's Fastest Memory Device at Intel Developer Forum; New XDR DRAMs from Toshiba and Samsung Provide 8x the Bandwidth of Today's Main Memory
- Synopsys and Intel Foundry Accelerate Advanced Chip Designs with Synopsys IP and Certified EDA Flows for Intel 18A Process
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |