Multicore designs might force Intel off its bus; Integrated memory controllers may loom large in future designs
By Tom Krazit, IDG News Service
December 16, 2004
As Intel moves in step with the rest of the chip industry toward the multicore design era, it is preparing to overhaul the memory bus architecture that has served it well for so many years, according to company executives and analysts.
Multicore processor designs are considered the solution to the performance scaling problem brought on by increased amounts of power leakage in modern chips. Transistors are now so small that increasing a chip's frequency, and therefore the amount of power it consumes, is not the simple exercise that kept companies like Intel going for many years.
However, in order to fully realize the performance gains provided by multiple processor cores, chip companies need to find a way to deliver enough data to the processor from the main memory to keep those cores as productive as possible.
Intel's current front-side system bus design should be able to keep as many as four cores satisfied, depending on the frequency of those cores, said Stephen Pawlowski, an Intel senior fellow, at a recent briefing on Intel's multicore strategy
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