It's become an accepted truth that to cost-effectively design a system-on-a-chip (SoC) will require embedded programmability. Yet few FPGA cores exist because it is not easy to develop one that works well and is efficient in silicon.
Trying its hand, FPGA supplier Actel Corp. Monday will unveil a variable-size programmable core that the company claims will consume 5,000 to 40,000 ASIC gates and little power, while delivering up to 250-MHz clock speeds.
The VariCore embedded programmable gate array (EPGA) was developed by ProSys Inc., which Actel acquired last year. Designed to work in a standard ASIC design flow, the core will offer Actel's customers a way to mitigate some of the high cost of building a complex SoC, according to the company.
As nonrecurring engineering fees rise and mask sets approach $1 million per mask, the top ASIC suppliers are pricing themselves out of the market, said John East, president and chief executive of Actel, Sunnyvale, Calif.
"By the time you get done with all the front money, you have to have big, big volume to justify the cost," he said. "That's fine for a few specialized applications, but most OEMs don't like that model."
Using a programmable core, however, will require more forethought in partitioning the design, according to East.
Analysts agree it will take time for ASIC designers to get comfortable with programmable cores. According to InSearch Research Inc., Phoenix, the embedded FPGA market will produce $30 million in revenue this year -- mainly engineering prototypes -- but it will be 2002 before the market starts to grow.
"The challenge will be making ASIC designers aware of how to use this capability," said Jerry Worchel, an analyst at InSearch Research. "Once they understand the advantages, including the ability to change designs on the fly or do evolutions of current designs, the embedded FPGA market could become quite large."
Dataquest Inc., San Jose, projects that by 2004, 80% of SoCs will contain some form of programmability.
To date, few viable FPGA cores have come to light. Agere Systems, Allentown, Pa., pioneered the technology with its ORCA FPGA family, but the core has primarily been used internally. Adaptive Silicon Inc., Los Gatos, Calif., is close to a commercial launch of its programmable core, which so far has been licensed only by LSI Logic Corp., Milpitas, Calif., the start-up's main stakeholder.
Actel's debut EPGA family is known simply as .18. The core is being qualified for manufacturing using 0.18-micron processes at Chartered Semiconductor Manufacturing Pte. Ltd., Taiwan Semiconductor Manufacturing Co. Ltd., and United Microelectronics Corp.
The .18 VariCore's architecture consists of primary embedded gate (PEG) blocks, each containing approximately 2,500 ASIC gates, along with interfaces for configuration, JTAG programming, and built-in self test. Optional RAM blocks can be cascaded to a depth and width of 512 Kbits ¥ 72.
The PEGs can be arrange d in arrays to fit a given design. A 4 x 4 array with 512 Kbits x 18 RAM would consume approximately 40,000 ASIC gates, or 206,000 system gates, said Yankin Tanurhan, director of embedded FPGAs.
"A standard FPGA trying to utilize the equivalent of 40,000 ASIC gates would have a die area two to three times bigger," he said.
The VariCores are placed and routed by Actel's VariCore Compiler, available in Windows NT and UNIX versions, and supported by leading EDA design, verification, and test tools.
The compiler is available; initial .18 EPGA cores and a developer's kit are slated for delivery in March. Actel plans to offer one-time and per-use licenses with back-end royalties based on units produced.