Breaks Power and Performance Barriers, Provides Complete Design Environment Hsinchu, Taiwan and San Jose, CA, December 29, 2004
- Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM), said today that its Nexsys 90 nanometer (nm) process continues a volume production ramp that will accelerate dramatically throughout 2005. TSMC’s Nexsys 90nm is the only foundry process at that node to feature copper interconnect, low-k dielectrics, and 12-inch wafer production as standard.
TSMC is already delivering 90nm products to industry-leading companies such as Altera Corp. and QUALCOMM, Inc., as well as multiple integrated device manufacturers (IDMs) around the world. The company states that it has reached several thousand 300mm wafers per month production level using Nexsys 90nm technology in the fourth quarter of 2004 and will ramp to higher volumes throughout 2005.
TSMC began 90nm volume production in the third quarter of 2004 following the successful delivery of numerous customer chips in first-pass silicon. The company anticipates that near 40 single-product mask sets will tape out in 2004 and that 30 more products will tape out on mask-sharing Cybershuttle wafers before year’s end. Among these products, close to ten have entered production stage and many others are either in qualification or design verification.
“TSMC expects that 90nm demand will increase at a rapid pace in 2005, across a range of applications in consumer, communications, PC and industrial markets,” said Dr. Genda Hu, vice president of marketing for TSMC. To support this strong demand, TSMC is preparing a major capacity expansion, and an aggressive ramp of 90nm technology in Fab 12 and Fab 14 during 2005.
“Our customers are designing to the 90nm Nexsys technology for a variety of reasons, including higher density and smaller chip size, faster performance, battery-saving lower power consumption, and lower die cost that is further enhanced by our 300mm production,” continued Dr. Hu. The Nexsys 90nm process has matured with very competitive defect density and process control. The TSMC DFM (Design for Manufacturing) offerings can help customers to reduce the time to volume production.
“Altera’s ramp of the 90-nm process is going extremely well and we are on track to have all six members of our Stratix II FPGA family verified for production by the end of the year,” said Francois Gregoire, vice president of Technology at Altera Corporation. “This smooth ramp is the result of three years of intense partnership, during which the design and process teams have worked closely together to solve all critical issues; including ‘design for manufacturability,’ low-k, power management, and performance optimization. The end result of this partnership is that Stratix II is unrivaled in terms of density and performance, and yields are better than any previous technology at the same stage.”
The Nexsys 90nm process provides a 2-times gate density improvement, 35 percent faster speed, 60 percent improvement in active power savings and a 20 percent interconnect RC improvement versus TSMC’s 0.13-micron process, based on a general-purpose ring oscillator. About TSMC’s Nexsys 90nm Process
TSMC’s Nexsys 90nm process is a full system-on-chip platform providing both CMOS logic and mixed-signal options with embedded high-density memories including 1TRAM 6TRAM, and 8TRAM. In addition, the new technology features multiple transistor types for improved power/speed/leakage tradeoffs.
The Nexsys 90nm logic family includes the high-volume general purpose (G) “G” process as well as low power (LP) and high-speed (GT) options. Each supports multiple Vt options including low, standard, and high. Operating voltage is 1-1.2V; the I/O voltages range from 1.8 to 3.3V, depending on family member. SRAM memory densities range from 1.65-micron2 to 0.99-micron2.
TSMC’s Nexsys process is supported by the industry’s most extensive portfolio of validated, process-proven libraries, including standard cells, SRAM, I/O and specialty libraries. Libraries come from Artisan, Nurlogic, Synopsys, Virage Logic and TSMC. TSMC libraries are distributed by Artisan, Cadence, Magma, Synopsys and Virage Logic. The Nexsys process is also backed by TSMC Reference Flow 5.0, the industry’s first reference flow providing critical power closure and integrated chip-to-package design for nanometer system-on-chip (SoC) integrated circuits. Building on the powerful dual-track methodology, which was built around major electronic design automation (EDA) developers Cadence Design Systems and Synopsys, Inc. and introduced in Reference Flow 4.0, the new reference flow includes significant new power management, design-for-test, design-for-manufacturing, flip-chip design capabilities, and the first integrated chip-to-package design capabilities. In addition to Synopsys and Cadence, Reference Flow 5.0 includes specialty tools from Mentor Graphics Corp., and newly introduced EDA partners Apache Design Solutions, Atrenta Inc., and Optimal Corp.
TSMC’s Nexsys 90nm technology is currently running in TSMC Fab 12 Phase I and will also be deployed in TSMC Fab 12 Phase II and TSMC Fab 14 as those 300mm production facilities ramp to production. About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com