Aldec Releases Integrated SystemC Debugging Environment with Assertion-Based Verification

Henderson, Nevada - December 27, 2004 -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new version includes additional SystemC debugging features, enhanced OVA/PSL/SVA assertion-based verification (ABV), and operating system-independent design libraries to support large designs which require verification on server farms across multiple platforms.

Integrated SystemC (TM) debugging

Riviera 2004.12 has extended the support for SystemC by allowing designers to instantiate VHDL and Verilog modules in SystemC code, providing complete coverage of all possible combinations of HDL and SystemC modules in the design hierarchy. The ability to instantiate HDL in SystemC, without the PLI/VHPI overhead or cumbersome wrappers, is essential to high-level testbench development in HDL. The latest release also includes the MinGW package. MinGW is an open source package that includes a GCC compiler and a GDB debugger, which allow designers to perform co-simulation with SystemC and HDL.

"This new functionality allows us to simulate any mix of VHDL, Verilog and SystemC design from one common debugging environment without the need to write a PLI and VHPI interface," stated Eric Seabrook, product marketing manager for Aldec. "Adding the ability to instantiate HDL in SystemC provides a completely new level of support from Aldec for system level design. This will allow engineers to utilize SystemC for testbench development for both their legacy designs containing HDL as well as new SystemC functional modules."

Assertion Based Verification (ABV)

A new assertion engine has been added which supports all three assertion languages including OpenVera assertions (OVA), Property Specific Language (PSL) and SystemVerilog assertions (SVA). The new assertions engine considerably reduces compilation and simulation times by compiling all assertions together with HDL modules. Designers can compile assertions as separate files or as an embedded description within the HDL source code. Assertion tutorials, samples, and template wizards are also included for additional ease-of-use.

Functional Code Coverage

In Riviera 2004.12, all assertion data can be collected and visualized in a new functional code coverage viewer along with the HDL code. New, dedicated assertion coverage views illustrate aspects of the design functionality that were, or were not, covered during verification. Functional coverage provides SOC designers with the added assurance that all the modules in their design have been tested for quality. Traditional structural coverage methods (code coverage, toggle coverage, branch coverage etc.) do not provide the functional test capabilities and offer a very limited understanding for the entire design under verification.

Platform Independent Libraries

Operating system-independent libraries provide design teams the added value of sharing compiled libraries across multiple platforms without having to re-compile. This saves considerable time and helps to overcome the issues that many companies have confronted when utilizing server farm methodologies based on different operating systems and architectures. Aldec's independent libraries support X86 for Windows® and Linux as well as Sparc for Sun® Solaris(TM).

Pricing and Availability

Riviera 2004.12 is available today based on a floating OS-independent license that supports UNIX, Windows® and Linux. Pricing for Riviera 2004.12 begins at U.S. $12,450.00 and is sold directly by Aldec in the U.S. as well as by authorized international distributors. For a FREE evaluation copy of Riviera, go to www.aldec.com/riviera.

About Riviera

Riviera, a high-performance verification tool, is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology and is used by ASIC and high-density FPGA designers for new generation system-on-chip designs. It supports IEEE VHDL 1076-87/93 and VITAL 2000 in addition to Verilog 1364-2001. Code coverage, Waveform Viewer, advanced dataflow, Design Profiler and interfaces to other EDA tools are provided via PLI and VHPI function calls as part of Riviera's product configuration.

About Aldec

Aldec, Inc., a 20-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.

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Riviera is a trademark of Aldec, Inc. SystemC is a trademark of the Open SystemC Initiative. All other trademarks or registered trademarks are property of their respective owners.