English
BOPS adds six patents
 |
BOPS adds six patents
By David Larner - Embedded Systems,
February 12, 2001 (2:05 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010212S0110
BOPS has been awarded six in a series of patents designed to protect its ManArray digital signal processing (DSP) core technology. The company has filed for more than 50 patents to date. BOPS' ManArray cores combine multiple levels of parallelism and use a single-cycle switching fabric between processing elements. The cores offer performances in range from 8bn operations per second (bops) to more than 128 bops at 200MHz. Patents awarded since February 2000 include: "Manifold array processor"(February 8, 2000) "Methods and apparatus for scalable instruction set architecture with dynamic compact instructions" (August 8/2000) "Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication" (November 21, 2000) "Methods and apparatus for ManArray PE-PE switch control" (December 26, 2000) "Methods and apparatus for manifold array processing" (December 26, 2000) " Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor"(January 9, 2001).
Related News
- ITC Judge Finds that SiRF Infringes Six Broadcom GPS Patents
- MOSAID Adds Patents to Complaint Against Micron,Powerchip,and ProMOS
- DVD licensing group adds audio player, recorder patents
- eASIC® Awarded Six Patents for Very High Density Configurable Logic Technology
- Cadence Design Services adds BOPS, Inc. to the Cadence Surelink Supply-Chain Network
Breaking News
- Revenue Ranking of Global Top 10 IC Design Companies Shows U.S. Companies Having Divergent Performances in 3Q19, Says TrendForce
- Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis
- CEA-Leti Builds Fully Integrated Bio-Inspired Neural Network with RRAM-Based Synapses & Analogue Spiking Neurons
- INSPECTOR diagnostic and debug platform passed the PCIe 4.0 compliance
- Aldec's new FPGA-based NVMe Data Storage Solution Targets High Performance Computing Applications
Most Popular
- Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors
- Cobham Releases RISC-V Processor IP Core
- Cobham Releases LEON5 Processor IP Core
- MediaTek selects Nucleus RTOS for next-generation modem technology
- Calterah Semiconductor's Automotive Radar SoC Enters Mass Production Using Synopsys DesignWare ARC Processor IP
|
E-mail This Article | 
|
|
Printer-Friendly Page |