Innovative Silicon launches new Z-RAM technology that doubles embedded DRAM density for SoCs

• Makes SOI lower cost than bulk silicon;
• Standard SOI logic process with no extra steps

Lausanne, Switzerland, Jan 24, 2005 --Innovative Silicon Inc. (ISi) has launched its Z-RAM™embedded memory technology for SoCs which doubles memory density when compared to existing embedded DRAM solutions. The Z-RAM (Zero Capacitor RAM) technology harnesses the Floating Body (FB) effect that occurs in Silicon-On-Insulator (SOI) devices, resulting in a cell structure that is based on a single transistor alone, rather than the combination of a transistor and a capacitor. Z-RAM memory designs have been taped out at 90nm and the technology is scalable to 22nm design rules. More, unlike other high density memory technologies, Z-RAM technology requires no extra mask steps, or exotic materials.

In SOI devices, the Floating Body or Body Charging effect which results in a charge developing in the FET device body has generally been considered as a parasitic effect. ISi has developed a mechanism to control and enhance this FB charge, which can then be used to store “1” or “0” binary states. Information is read by comparing the current in a selected cell to a reference, using a current sense amplifier.

SOI is emerging as the process technology of choice for high performance SoCs and Microprocessors, with leading processor and games companies already switching away from bulk CMOS to take advantage of the increased performance and reduction in power that SOI delivers. Explains ISi CEO, Mark-Eric Jones: “Embedded memory occupies at least 70 per cent of the die area of today’s complex SoCs. The combination of our Z-RAM memory – which requires less than half the die area required for traditional embedded DRAM, without the additional process steps required to embed traditional DRAM – and existing SOI processing, which additionally offers large performance and power benefits, means that not only are Z-RAM SoCs higher performance and lower power, they are also much cheaper than SoCs based on bulk CMOS wafers.”

He continues: “By reversing the traditional economics and making SOI wafers a lower cost solution than bulk silicon for most SoCs and microprocessors, we expect our Z-RAM memory technology to accelerate the anticipated industry switch from bulk silicon to SOI. As a result designers of cost-sensitive products will also be able to take advantage of the increased performance and lower power consumption of SOI.”

Finally, Z-RAM technology does not require designers to compromise on speed or power: read and write operations in under 3nS have already been demonstrated on silicon; while ISi’s low power Z-RAM option promises significant power savings compared to traditional embedded DRAM.

Concludes Jones: “Since Z-RAM technology uses a single transistor and no capacitor in the bitcell it is much more scalable than alternative DRAM and SRAM technologies. We have already demonstrated a Z-RAM memory cell using FinFET technology and expect Z-RAM to easily meet the high density embedded memory requirements of chip designers for the next 15 years.”

About Innovative Silicon
Incorporated in 2002, Innovative Silicon was founded to develop and commercialise Floating Body effect memory for SoC/MPU products used in diverse applications including handheld computers, games consoles, cellular communications devices, cameras etc. The company closed its first round of VC funding in 2003 and taped out its first 90nm megabit Z-RAM memory designs in 2004. The company is incorporated in the USA with an R&D facility in Lausanne, Switzerland.
www.z-ram.com