EDA Tool Maps Complex ANSI C And SystemC Algorithms To Optimized SoC Implementations Generates High Performance DSP Co-processor Architectures for 3G Applications
JANUARY 30, 2001, EDS, ASP-DAC, YOKOHAMA, JAPAN - Frontier Design today unveiled its Version 2.2 of its A|RTTM Designer architectural synthesis tool. A|RT Designer is ideal for the design of ASICs and high density FPGA system-on-a-chip implementations of ultra high performance, low power DSP applications such as MPEG4, turbo codecs and IMT-2000 for WCDMA. The tool lets designers derive and explore multiple hardware architectures from system-level, fixed-point SystemC and ANSI C algorithms.
Ideal for 3G Designs
According to Herman Beke, Frontier Design's CEO, "Today, a typical GSM phone must execute 60 million instructions per second and an IS-95 or CDMA phone must execute 80 MIPS. Next generation 3G phones will have to support video compression and decompression, accommodate Internet browsers, support email, run Java applets, and conceivably support MPEG4 and MP3 processing. That's a great deal more processing and will require a great deal more processing power in a very small about of space with severely constrained power consumption.
In fact, a typical 3G WCDMA phone is expected to require 350 MIPS of processing just for channel coding and decoding tasks. Since a low-power DSP can only handle about 150 MIPS maximum, increasingly handset designers are moving toward the development of baseband co-processors to handle the more repetitive and compute-intensive tasks, such as the processing of turbocoders and voice codecs. Due to the very nature of the application, these co-processors must be highly optimized to achieve exceptional throughput while consuming a minimal amount of power.
"A|RT Designer 2.2 gives designers the flexibility and power to achieve highly optimized SoC implementations of DSP algorithms that will be used in 3G co-processors. For example, A|RT Designer 2.2 was used to create a hardware implementation of a Viterbi decoder from ANSI C code. The default architecture required 13,750 cycles for execution and required 15,600 ASIC gates. Using A|RT Designer's analysis and optimization capabilities the design was reduced to 7,100 ASIC gates and required only 425 clock cycles to execute. The estimated power consumption was reduced by 98.6%. Clearly, this is the ideal tool for the implementation of 3G handsets" Beke concluded.
Seamless SystemC and ANSI C Design Capability
A|RT Designer 2.2 allows DSP-based system designs to be done at a very high level in MATLAB®, SPW® or COSSAP®, and taken all the way to a synthesizable Verilog or VHDL description, using the SystemC or ANSI C languages. Floating point ANSI C-code can be refined to fixed-point SystemC code either manually or automatically, using tools such as Synopsys' (NASDAQ:SNPS) CoCentric® Fixed-Point Designer. The fixed-point SystemC description is read directly by A|RT Designer without any "language" penalty usually associated with going from a system-level language to an RTL implementation. A|RT Designer is then used to explore architectural alternatives and, when the optimum architecture is found, automatically generates Verilog or VHDL.
The designer has complete control of the process and can specify which resources will be used in the design, including ALUs, multipliers, adders, RAM, ROM, and registers. The tool lets designers create application specific resources that can perform multiple operations in a single clock cycle. The tool uses a patented "dataflow analysis" technique that automati-cal-ly iden-tifies and exploits data dependencies in the code to maximize parallelism in the hard-ware de-sign. A|RT Designer assigns operations to these resources based on the dataflow analysis. A|RT Designer then generates a VLIW controller and datapath that schedules the operations on the hard-ware resources. The designer may modify the architecture, scheduling or resource allocation at will, using pragmas that are created using an embedded pragma editor. Because A|RT Designer is not overly constrained, design iterations are very fast. For example, generating an architecture and analyzing the results for a 7,000 line C-language design can be accomplished in less than 1.5 hours per design iteration.
Library Creation Tool Fosters Design Re-use
A|RT Designer 2.2 comes with a predefined library of data path resources, such as adders, multipliers, ALUs and registers. However, many designers prefer to develop their own resources. For example a ripple carry multiplier may be most efficient in one design, while a Booth's recoding algorithm multiplier may work best for another. The designer may create multiple libraries with specialized resources. A|RT Designer 2.2 lets designers add resources they have designed themselves, as well as creating new resources. The user interface lets the designer describe how the resource is related to various functions in the C code, where the inputs should go, where the outputs should go, and how inputs and outputs relate to each other in time. That way designers can easily specify complex single- cycle, multi-cycle and/or pipelined resources.
Mapping C-code onto Specially Created Application Specific Resources
A|RT Designer 2.2 aides designers in developing application specific hardware resources that can accelerate the execution of complex DSP algorithms such as FFT and MPEG by one or more orders of magnitude. This feature is not available in any other EDA tool on the market today. Most synthesis tools map the algorithm to standard library resources such as adders, multipliers and shifters, resulting in a less than optimum implementation. A|RT Designer 2.2 allows designers to create special resources that execute several operations in a single clock cycle. Several operations can be combined into a single-cycle "super" instruction that can be executed by the special resource, substantially increasing system performance.
For example, an FFT butterfly that requires two multiplications, an add and an accumulation (check what butterfly is) would take at least four clock cycles to complete using conventional ALUs, multipliers and registers. By developing a special resource that executes the two multiplications, addition, and accumulation, the super instruction can be executed in a single cycle. Using conventional library resources a 1024 point FFT would require 4096 clock cycles. Using the special resource and super instruction, the 1024 point FFT can be executed in just 1024 clock cycles.
Once the special resource and super instruction have been defined, the designer defines a wildcard template that ties the special resource to the appropriate super instruction. The tool then automatically performs a pattern search on the C-code and maps all matching expressions to the special resource.
A|RT Designer 2.2 provides a view of the system architecture that includes all resources and busses and how they relate to operations in the C-code. The resources can be clicked on to highlight interconnect to other resources and as an index into the more detailed design reports. The architecture view is useful in identifying bottlenecks, under utilized resources, and bus congestions.
Elaborate Suite of Optimizations
A|RT Designer 2.2 can perform advanced transformations and architectural optimizations, either globally or in specific local sections of the design. These optimizations include, but are not restricted to alternative sche-duling strategies, loop folding, time loop folding, peephole optimization, and speculation.
Extensive reports and graphical analysis tools embedded in A|RT Designer provide the designer with comprehensive information about the design, including 1) the number of cycles required to execute every part of the code (e.g. loop bodies, function calls, etc.); 2) resource and register allocation and utilization; 3) variable lifetimes, register transfers, and 4) memory utilization. The tool offers cross highlighting between all views, so clicking on an execution bottleneck, for example, will highlight the corresponding schedule of register transfers and the associated C source-code. A built-in pragma editor with extensive help utilities allows designers to add or remove specific data path resources (e.g. an ALU, a multiplier, a memory, etc.), assign particular operations to particular resources, or alter the scheduling of operations according to different strategies (ASAP, ALAP, or ALAP Greedy).
A|RT Designer 2.2 is available now with several different pricing alternatives. Prices start at $45,000 (US list price).
Frontier Design was founded in 1997 as the result of a management buy-out of the European Development Center of Mentor Graphics (Nasdaq:MENT). The firm's primary emphasis is its "algorithm-to-silicon" design methodology that greatly improves the creation of Silicon IP blocks starting from customer-proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications. Algorithm-to-Silicon IP blocks consume less power, are less costly and require substantially less development time than other alternatives. Frontier Design sells its design services and a line of EDA tools directly from its facility in Leuven, Belgium, and from its sales office in California. Frontier Design also sells through a growing number of distributors and Value Added Resellers in Northern America, Europe, Japan and the Pacific Rim.
Frontier Design's World Wide Web site is http://www.frontierd.com. Email inquiries may be sent to firstname.lastname@example.org.
A|RT is trademark of Frontier Design. CoCentric MATLAB, SPW and COSSAP are registered trademarks of the companies that own them.