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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Temento Systems announces the release of DiaLite Platform Edition introducing PSL On Chip Verification (OCV)
Montbonnot, France, February 23, 2005 – Temento Systems is announcing at DATE 2005, a new version of its innovative DiaLiteTM debugging tool: The DiaLiteTM Platform Edition.
A PSL Assertion Checker module is now available to enable At Speed properties verification, directly on the chip. Major features and improvements include PSL 1.1 language support, PSL IP automatic generation and insertion and PSL debug manager. This Edition takes advantage of the DiaLiteTM Instrumentation benefits and complex PSL functions can be associated with triggers IP cores. Combining the instrumentation IP cores on a same platform enlarge the debug possibilities like never done before.
PSL On Chip Verification (OCV) will allow designers to create PSL properties (A Boolean & temporal set of expressions describing system behaviour) that address their design checking requirements. Translation of PSL properties into VHDL/Verilog languages enable to generate IP Assertion Checker Verification Units (ACVU) which are then embedded into the user's design. The verification is performed directly on the chip and runs at design speed.
Another major benefit is offered with PSL incremental analysis capability which enable to progress in the debug without being obliged to do several synthesis loops. Bringing PSL High Level systems specifications on chip allows to detect critical bugs earlier and faster.
Working with assertions provides more information and can drastically improve the understanding of the internal behavior of the design. Implementing DiaLiteTM PSL Assertion Checker as part of the design process will create in any case a considerably higher quality of design and speed up time-to-market.
Pricing and Availability
Release 4.5 of DiaLiteTM Platform Edition is available now on Windows XP, 2000/NT and Solaris. Subscription licenses start from €15 000.
About Temento Systems
Temento Systems S.A. provides Electronic Design and Test Automation (EDTA) solutions that enable engineers to test and debug electronic products, including System on Chip (SoC), FPGAs, Boards, Multi-Chips Modules (MCMs) and Systems. Unlike traditional EDA software providers, Temento Systems offers a broad range of solutions focused on systems design test, starting from the earliest stage of design definition (virtual test), straight through hardware testing (physical test).
http://www.temento.com
The Temento Systems name and logo are trademarks of Temento Systems Corporation.
All other trademarks and service marks are the property of their respective owners.
A PSL Assertion Checker module is now available to enable At Speed properties verification, directly on the chip. Major features and improvements include PSL 1.1 language support, PSL IP automatic generation and insertion and PSL debug manager. This Edition takes advantage of the DiaLiteTM Instrumentation benefits and complex PSL functions can be associated with triggers IP cores. Combining the instrumentation IP cores on a same platform enlarge the debug possibilities like never done before.
PSL On Chip Verification (OCV) will allow designers to create PSL properties (A Boolean & temporal set of expressions describing system behaviour) that address their design checking requirements. Translation of PSL properties into VHDL/Verilog languages enable to generate IP Assertion Checker Verification Units (ACVU) which are then embedded into the user's design. The verification is performed directly on the chip and runs at design speed.
Another major benefit is offered with PSL incremental analysis capability which enable to progress in the debug without being obliged to do several synthesis loops. Bringing PSL High Level systems specifications on chip allows to detect critical bugs earlier and faster.
Working with assertions provides more information and can drastically improve the understanding of the internal behavior of the design. Implementing DiaLiteTM PSL Assertion Checker as part of the design process will create in any case a considerably higher quality of design and speed up time-to-market.
Pricing and Availability
Release 4.5 of DiaLiteTM Platform Edition is available now on Windows XP, 2000/NT and Solaris. Subscription licenses start from €15 000.
About Temento Systems
Temento Systems S.A. provides Electronic Design and Test Automation (EDTA) solutions that enable engineers to test and debug electronic products, including System on Chip (SoC), FPGAs, Boards, Multi-Chips Modules (MCMs) and Systems. Unlike traditional EDA software providers, Temento Systems offers a broad range of solutions focused on systems design test, starting from the earliest stage of design definition (virtual test), straight through hardware testing (physical test).
http://www.temento.com
The Temento Systems name and logo are trademarks of Temento Systems Corporation.
All other trademarks and service marks are the property of their respective owners.
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