 |
VSIA releases functional verification taxonomy
By Michael Santarini, EE Times
January 29, 2001 (5:50 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010129S0037
SAN MATEO, Calif. — The Virtual Socket Interface Alliance has released a taxonomy document that defines terms related to the functional verification of intellectual property cores or virtual components, and classifies functional verification tools and technologies. The release of the taxonomy is a step toward creating standards and guidelines for functional verification as it relates to cores, said Timothy O'Donnell, president of VSIA (Los Gatos, Calif.). "Before you get down to the business of creating specifications, you have to be sure that everyone is using the same terminology," O'Donnell said. "The taxonomy [creates] a level playing field so everyone can move forward and make progress on standards a lot more quickly." Thomas Anderson, co-chair of VSIA's Functional Verification Development Working Group, said the Taxonomy of Functional Verification for Virtual Component Development and Integration Version 1.1 defines, indexes and c ross-references different methods and attributes of functional verification, specifically for cores and system-on-chip (SoC) devices containing cores. The document breaks down tools and techniques for four main types of verification: intent verification, equivalence verification, virtual component verification and integration verification. Under intent verification, the taxonomy provides a detailed description of techniques that enable designers to verify the intended functionality of a design and establish a reference model throughout the design process. They include dynamic verification, formal verification and emerging hybrid techniques. For equivalence verification, the taxonomy covers techniques for ensuring a functional match between the reference model and the various design levels created throughout the development process. The document also defines processes for verifying the functionality of a standalone core via verification of virtual components and core-based SoC designs via integration verification, said Anderson. The next step for the working group, Anderson said, is to create a formal specification the defines the deliverables related to functional verification that would go along with a virtual component. "We plan to create a guideline or list of recommendations that virtual component vendors should be providing to customers," said Anderson. "It will also prepare engineers for what they should expect from virtual component vendors." The taxonomy can be downloaded from the VSIA Web site. A summary of VSIA functional verification definitions is available online at EEdesign.com.