| Monterey, Calif. — A panel representing the equipment, EDA, foundry and fabless semiconductor industries teased out the challenges of manufacturing at 65 nm and beyond at the GlobalPress Summit here. |
While the attitude was positive, no one wanted to understate the work still to be done in making 65 nm a viable manufacturing technology. And no one was willing to claim any clear vision of what might await us beyond the 45 nm node.
Mark Pinto, a senior vice president & chief technical officer at Applied Materials, led off the discussion by stating, "The nature of the equipment industry's contribution has changed at recent nodes," he stated. "We cannot simply provide a machine any more. Today, we must be involved in a broad collaboration that brings in materials research and development and a certain level of process development as well."
But given the reality of cross-cultural collaboration, Pinto said that the 65-nm node didn't appear to be disruptive. There would be no initial introduction of new materials or process steps—just a refinement of what was learned at 90 nm, and widespread use of strain engineering to improve channel mobility.
For 45 nm, however, Pinto was more cautious. He foresaw the introduction of high-k materials, increased struggles with design-for-manufacturing technology and issues with overall cost of ownership for designers—none of these issues currently solved.
Speaking from an EDA point of view, Ted Vucurevich, CTO at Cadence, offered a similar time line for different reasons. Vucurevich focused not on processes, but on models, which he described as the interface between the manufacturing and EDA worlds. And those models are becoming so complex that they require early, intimate engagement between EDA developers and process developers, he said, warning that the EDA industry may have begun to work on 65 nm two years too late.
Vucurevich said that the old approach—building static models of devices, protecting them with guard banding and incorporating them into back-end tools—was failing. Instead, EDA developers are having to build models that took into account the three-dimensional pattern dependencies from which process variations spring, identify which patterns can be made to fall within a reasonable level of electrical parameter variance, and incorporate this data early in the design flow. The idea, he said, was to create patterns that are known to work early in the flow rather than trying to fix whatever comes out of synthesis, place and route with post-processing reticle enhancement techniques.
"I think 45 nm will be our real problem child," he said. "At that point the pattern dependencies become severe, and we have to move to whole new concepts such as in-situ validation of electrical parameters."
John Martin, vice president of strategic alliances at Chartered Semiconductor, brought an independent foundry view to the discussion. "We are in a transition period," Martin said, "from the days when moving to a new process node primarily meant device scaling to a time when moving to a new node can only be accomplished with wide-spread innovation.
"This innovation isn't just in process technology," he continued. "It has to take place in circuit design and tool development as well. It means everyone working together."
Beyond 65 nm, Martin predicted, we would see new materials introduced again, particularly in the gate stack, with their attendant learning curves. New transistor structures would emerge as well, he said, to achieve an acceptable combination of drive current and leakage current. And with those changes would come changes in circuit and cell design techniques, changes in the approach to defect management and a new emphasis on process controls.
Fumitomo Matsuoka, senior department manager at Toshiba System LSI Division I, added the integrated device manufacturer's perspective. "There are many roadblocks between us and further production," he said. "One of them is a power-performance crisis. After 45 nm, we will see designs where standby current will dominate the overall power consumption of large chips.
Another roadblock," Matsuoka continued, "lies in the problem that the markets we are now serving require a very fast manufacturing ramp. But the very complexity that makes these products possible means that ramping is difficult. Further, costs are becoming huge. Complexity costs money—even the equipment we must buy is hugely expensive," Matsuoka said with a glance toward Applied's Pinto. "I think maybe we can achieve full production through 45 nm, but to do that circuit designers will have to help with issues like power."
Daniel Gitlin, senior director of technology development at early-adopting giant Xilinx, brought the user's perspective. He said that to keep a year ahead of the ITRS roadmap, Xilinx had to form just the sort of early, intense partnerships with EDA and foundry vendors that Vucurevich had described. Even so, he said, the company faced dual problems.
On the one hand, he warned, pattern-related variations were increasing, making circuit design and modeling vastly more difficult. At the same time, continuously dwindling supply voltages—decreasing much faster than threshold voltages—have narrowed the design window to the point that only about 0.7V is left for circuit designers to employ.
"I think at 65 nm we see a fork in the road," he maintained. "Already it has become impossible to continue scaling oxide thickness. Instead we are turning to mobility engineering, and eventually to new gate stacks. But these techniques in turn are creating more severe layout dependencies. Yet we will continue. The job of process engineering is to make all the revolutionary things that have to be done appear evolutionary."
Asked about the future of optical lithography, the panel expressed confidence—up to a point. "The roadmap is still 193 nm, with immersion optics and high Numerical Apertures, perhaps as far as the 32 nm node," Pinto said.
But Vucurevch rejoined that every move to push 193 nm lithography further meant more aggressive optical proximity correction, more issues with pattern-dependent effects, and a vast increase in data size and computing loads. "This is more than we can do with simple post-processing," he warned. "These tasks will have to be moved earlier in the design flow."
Gitlin added that in an attempt to deal with these problems through conventional techniques, "the number of design rules in a process appears to follow its own Moore's Law, increasing by a factor every generation. Improved EDA tools have to absorb this complexity."
Matsuoka agreed, saying that rule-based optical proximity correction would have to be abandoned for a model-based approach after the 65-nm node. He agreed also that we could stay with optical lithography, possibly through 32 nm, and that Fujitsu planned to use ArF light sources with immersion optics for 45 nm.