| MONTEREY, Calif. — Executives and marketing managers from the EDA, intellectual property and design consolidation businesses debated the course of SoC design at a GlobalPress Summit panel here. After spirited discussion they declined to agree on a single theme. |
Leading off the discussion, Jack Harding, chairman, president and CEO of eSilicon, spotlighted manufacturability as the key issue in SoC design.
"There is a misconception that we have a design problem in SoC design," Harding opened. "It's not a design problem but a simultaneous design and manufacturing problem—two issues that have to be addressed together.
"For instance, at eSilicon we don't look at the interval from start of design to tape-out as an interval. Rather we work with our customers over three intervals: start-to synthesis, synthesis to prototype and prototype to end-of-life. If you break down those barriers between design and manufacturing, then the challenges in SoC design are not great today."
While Harding focused on the integration of design with manufacturing, the next speaker, Dave Kelf, VP of marketing at Novas Software, turned the spotlight on the architecture of the SoCs themselves. Kelf argued that we are in a transition period during which the fundamental architecture of SoCs was shifting, away from the central processor with accelerators and peripherals toward distributed processing on a heterogeneous collection of processing sites.
"We are coming to a time of relatively fixed hardware, with the application functionality coded in software," Kelf said. "The big question soon will be how to design the first kiloprocessor system."
Kelf said that the biggest parts of this challenge will be mapping application code across the heterogeneous mix of processors and, not surprisingly, verification.
Tom Peterson, director of product marketing at MIPS Technologies, echoed Kelf's claims. "The real challenge will be mapping of application code onto multiple threads or multiple kinds of processors," he said. "Imagine a time when the functionality you see on your TV set is provided by Java applets rather than hardware."
Tensilica VP of marketing Steve Roddy added his assent as well, saying "the risk and complexity today are in creating hard-wired logic to perform critical functions. This is removed by moving the functionality to software running on a collection of application-optimized processors."
What was at that point threatening to become a multiprocessing love-fest was chilled somewhat by ARC International CEO Carl Schlachte. "The thought of a Java-enabled TV set terrifies me," he began. "It all sounds very appealing. But when you talk to the players in the consumer electronics industry, for example, the first thing they are demanding is hardware-based differentiation."
Peterson stepped in to agree, somewhat surprisingly, since he had just floated the idea of a Java-based TV set. "You have a system here that downloads applets and executes them to create functionality visible to the user. Frankly I have no idea how to test it."
Schlachte had words for the supposed elegance of multiprocessing, as well. "The advocates of heterogeneous multiprocessing talk a great story. But the bulk of the problem isn't putting a bunch of CPUs together—it's verification. Those CPUs must play nicely together. But today, with the tools most people are using, these heterogeneous multiprocessing environments aren't plug'n'play. It's more like plug and pray."
Asked if FPGAs represented an important alternative approach to SoC design, the panel reacted with almost scornfully. "The FPGA community is an awesome marketing engine," Harding said. "But they represent two per cent of the semiconductor market. The limitations of FPGAs pretty much offset any notion of them as an SoC platform except at very low volumes."
Returning to the question of flows, Peterson offered that the next big change in SoC design wouldn't be the move to ESL-based hardware-software co-design. This in turn led to some discussion of whether the tools for such flows would come from the EDA industry or from processor IP vendors themselves, as appears to be increasingly the case with ARC and Tensilica.
"The reason these people are being drawn into making tools is that the EDA industry is broken," Harding proclaimed. "When designers have to buy licenses at the beginning of a design, it's a tax on design, not a partnership in the success of the project." Harding said eSilicon had offered to work with all of its EDA vendors on a royalty basis, but all had declined.
Kelf, surprisingly, agreed. "We need to change our business models. In fact, Novas has taken some royalty deals. The fact is that there is no way we can progress if we don't throw away the boundaries between EDA and design teams and work together."
"But the huge elephant in the room that we are all trying to ignore," Schlachte rejoined, "is not the divide between vendors and users. It's the divide between the hardware and software developers within the user organizations. Customers have to accept bridging of that wall before they can make progress in these architectures."
"But that will take reeducation, and major reorganization in many companies," Roddy warned. Those are always fallen words for a marketing plan.