Faster, scaleable and more efficient on-chip communications for complex SoCs enabled by Arteris NoC SolutionTM
PARIS, France — 14 March 2005 —Arteris SA, a start-up founded by communications chip industry veterans and focused on the challenge of on-chip communications, today unveiled its first product offering, a complete solution for creating Networks-on-Chip (NoC). Arteris NoC SolutionTM is used to connect and manage the communication between the variety of design elements and intellectual property (IP) blocks required in today's complex system-on-chips (SoCs). The company's proprietary IP library utilizes a packet-based switch fabric in conjunction with Arteris NoC specific design tools to generate unique NoC instances. The result is the first commercial NoC solution that overcomes the limitations of traditional bus-based methods, while maintaining compatibility with existing interface standards and design tool flows.
While NoC has been an emerging area of academic and research interest, Arteris is the first to offer a commercial solution for chip designers. Like the networking of computers, NoC provides an efficient means to manage communications among any collection of distributed systems, which in the case of a complex SoC can be individual IP blocks and/or clusters of functionality that all must communicate with each other. The proliferation of tens, even hundreds, of IP blocks on a single chip, as well as the advent of ultra-thin line widths in deep submicron processes, have made traditional on-chip communications methods such as buses an increasingly substantial obstacle in the way of realizing the full potential of SoC implementations.
To enable improved system performance, achieve critical timing requirements, and facilitate more efficient IP use (and re-use), Arteris' solution borrows applicable networking techniques and implements them in its NoC Solution. The solution uses fundamental networking units, such as switches and links, in the form of configurable IP blocks, combined with design exploration and compilation tools that generate the completed NoC for common design tool flows, in the form of high-level description formats such as SystemC and synthesizable Verilog or VHDL. Arteris' proprietary packet-based NoC Transaction and Transport Protocol (NTTP) ensures compatibility with all major on-chip SRAM blocks and socket standards (AMBA AHB, AMBA AXI, OCP 2.0), and also supports key off chip interfaces such as Denali's DatabahnTM DDR memory controller IP. A point-to-point physical implementation leverages the Globally Asynchronous Locally Synchronous (GALS) paradigm, with demonstrated operating frequencies of 750 MHz or more in 90nm silicon process, using standard cells libraries and off-the-shelf EDA tools.
Among the high level benefits of Arteris' NoC Solution are:
- Improved on-chip communication throughput and quality of service resulting into higher SoC performance
- Improved complexity/cost ratio to manage the increasing number of transactions on a complex SoC, and scale with future requirements
- Improved efficiency of silicon area through the optimal use of on-chip resources dedicated to IP communications
- Improved designer productivity by speeding IP integration and re-use, facilitating more efficient design, and providing a faster path to timing closure
"On-chip communications is increasingly the most critical challenge in developing complex SoCs. Current approaches simply do not scale with the global wire delay and IP integration issues present on today's feature-rich and IP-laden chips. What is required is a true network on a chip that treats the SoC as a complete system with a variety of local requirements, all of which need to coordinate at the system level," said Alain Fanet, president and CEO of Arteris. "We have taken lessons learned and technologies developed in the computer networking area and applied them to chip-level design. Many of the concepts are almost identical, and our challenge has been to implement them on-chip in a way that achieves the benefits of a true NoC, while being cost-effective in terms of gate and wire area and as non-disruptive as possible to existing design methodologies. With Arteris NoC Solution, we are confident we are offering a very viable and effective approach to this new class of on-chip communications requirements."
Arteris NoC Solution
Arteris NoC Solution consists of the Danube Intellectual Property Library that contains a set of configurable building blocks managing all on-chip communications between IP cores in SoC designs, and a suite of design tools for configuring and implementing the IP library as synthesizable RTL.
The Danube IP library is comprised of three types of units: Network Interface Units providing interfaces to the IP cores, Packet Transport Units and physical links building up the switch fabric user-defined topology. These units can be configured based on the system objectives and topology requirements. The building blocks implemented in Danube IP use a GALS method to span distance and cross clock boundaries on the chip. An on-chip protocol 'spy' is provided for runtime system-level debug.
The NoCexplorerTM exploration tool provides an intuitive and robust environment to capture the dataflow requirements of the IP blocks to be serviced by the NoC and allows the designer to rapidly analyze various NoC topology options to achieve optimal performance and area implementation. It utilizes a very fast dataflow simulation engine and parameterizable dataflow sources and sinks to model the system behavior.
The NoCcompilerTM design tool creates a database of the specific instance of the NoC. It generates a variety of views of the NoC, in Verilog, VHDL, SystemC, or other standard formats including synthesis scripts. NoCcompiler provides capabilities to ensure design consistency across multiple versions, rules checking, and pre-synthesis area estimation. It produces a datasheet of configured NoC units, including a register map. NoCcompiler's outputs are compatible with standard ASIC design flows, including a SystemC cycle-accurate model, synthesizable RTL descriptions, FPGA-optimized output for system prototyping, and synthesis scripts.
Pricing and Availability
The Danube NoC IP Library is available as a licenseable IP and pricing is based on customer-specific use requirements. Arteris NoCexplorer and NoCcompiler are priced separately and are available for either Linux or Sun Solaris (version 8).
Arteris, SA, provides Network on Chip solutions to transport and manage the on-chip communications within complex System-on-Chip (SoC) integrated circuits, increasing performance while enabling the most complex IP-laden designs. It allows chip developers to implement efficient and high-performance Network-on-Chip (NoC) designs, overcoming limitations of traditional interconnect approaches such as layered or pipelined bus-based architectures. Arteris' technology is scaleable in terms of the number of IP blocks designers can network, as well as with silicon manufacturing process evolution. The NoC solutions are compatible with existing design flows and with IP interface standards. The Paris-based company was founded by semiconductor industry veterans and is backed by an international set of venture capitalists. Arteris has raised more than $12 million in early funding from an international set of venture capitalists, including Crescendo Ventures, Techno Venture Management and Ventech. More information can be found at www.arteris.com.