Versions Optimized for Low-Power, Small Silicon Footprint or for High-Performance, Dual-Data-Rate Applications
SAN FRANCISCO, Calif., March 7, 2005 - Toshiba America Electronic Components, Inc. (TAEC)* today announced a new family of 1.5 gigabit per second (Gbps) and 3Gbps Serial ATA (SATA) PHY cores to support the SATA and Serial Attached SCSI (SAS) specifications for the 130 nanometer (nm) process node. The cores support a wide range of application requirements in desktops, mobile and consumer electronics, servers and networked-storage environments. Versions have been optimized separately for a low-power, low-cost small silicon foot print or for high-performance, dual data rate applications. The cores are currently available for customer design-in.
"Toshiba is committed to providing the silicon-proven, high-speed interfaces required for the custom SoC market and our new family of SATA PHY cores is an example," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. "The cells were developed by our North America-based high-speed input/output (HSIO) and mixed signal development team and are supported by our dedicated team of customer-focused application engineers." Mr. Tobias explained that this engineering capability and customer support is vital since the PC board traces of the final end product are a design consideration in custom SoC designs for high-speed I/O applications: "You can't just take for granted that the HSIO circuit will work to spec when you plug into a real-world circuit. Our engineers work with the customer's hardware designers to ensure that their SoC will deliver the performance they need."
SATA ATA is an evolutionary replacement for the Parallel ATA physical storage interface. The Toshiba cores are compliant with the SATA 1.0 and SATA II Gen1 i, m, and x and Gen2 i, m and x electrical specifications and support the SCSI standards. The low-power, low-cost version is optimized for 1.5Gbps (Gen1) applications while the high-performance core has been optimized for both 1.5Gbps and 3.0Gbps (Gen2) applications. The highly flexible cores were designed with many programmable operating characteristics and can be configured as either device or host. Support macrocells such as phase-locked loops (PLLs), clock generators, buffers, band gap, bias current and calibration circuits are implemented separately, allowing them to be shared in multi-channel applications to minimize die area and power consumption.
- Implements Out of Band (OOB) signaling and control state machine
- Data rate negotiation with Gen2 (3.0Gbps) or Gen1 (1.5Gbps) devices
- Optional fixed data rate at Gen2 or Gen1
- Low power, small footprint CDR
- Configurable as Device or Host
- Programmable OOB sequence bypass
- Supports Spread Spectrum Clocking (SSC) for EMI reduction
- Amplitude programmable differential serial output enabling support for both SATA and SAS (i, m and x) applications with optimal power
- Programmable serial output half or full bit pre-emphasis
- Programmable serial data transmit or receive polarity inversion
- Programmable serial receiver squelch sensitivity
- Built-in self-test pattern generator and checker
- Line and internal loop back modes of operation
- 10-bit or 20-bit parallel interface with link layer
- PHY designed as a single large I/O cell with all I/O pads included
- Digital CDR Architecture for low power and portability
- Digital equalization filter for receiver jitter tolerance improvement
- Shared support macro cells for low power in multi-channel designs
- SATA OOB signal detection, transmission and handshaking
- 150/75 megahertz (MHz) register-to-register type interface to ASIC core on both receive and transmit interfaces
- Other available macro cells include the following and can be shared in multi-channel designs
- 1.5 gigahertz TX-PLL for transmit high-speed clock generation.
- 750MHz multi-phase RX-PLL for receiver high-speed clock generation.
- Band-gap and bias current circuits.
- Calibration circuit for on chip termination resistors.
- Reference clock input buffer.
About the 130nm TC280 family of SLI ASICs
The TC280 family of System-Level Integration (SLI) ASICs is designed for applications needing high performance with the small die size. The 130nm ASIC family employs high-density gates, memories, I/Os and interconnect structures and is well-suited for systems above 200MHz or 5 million gates. Three library options for low power, high speed and very high speed may be mixed and matched in designs to permit optimum performance with a smallest die size and low power. Toshiba also offers two types of embedded DRAMs. The 250MHz SD type is targeted for high-bandwidth, large-memory block applications and the fast access FA type for SRAM replacement. These embedded DRAM cores are based on Toshiba's production-proven trench capacitor technology, which permits mixing of logic and DRAM without degrading logic performance.
The SATA PHY cores are currently available for customer design-in. An evaluation board is expected to be available in April 2005. Volume production is planned to start in the third quarter of 2005.
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, and displays for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba Corporation, one of the five largest semiconductor companies worldwide in terms of global sales for the year 2003 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com.