SAN FRANCISCO, Calif., March 7, 2005 - Toshiba America Electronic Components, Inc. (TAEC)* today announced a new family of 1.5 gigabit per second (Gbps) and 3Gbps Serial ATA (SATA) PHY cores to support the SATA and Serial Attached SCSI (SAS) specifications for the 130 nanometer (nm) process node. The cores support a wide range of application requirements in desktops, mobile and consumer electronics, servers and networked-storage environments. Versions have been optimized separately for a low-power, low-cost small silicon foot print or for high-performance, dual data rate applications. The cores are currently available for customer design-in.
"Toshiba is committed to providing the silicon-proven, high-speed interfaces required for the custom SoC market and our new family of SATA PHY cores is an example," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. "The cells were developed by our North America-based high-speed input/output (HSIO) and mixed signal development team and are supported by our dedicated team of customer-focused application engineers." Mr. Tobias explained that this engineering capability and customer support is vital since the PC board traces of the final end product are a design consideration in custom SoC designs for high-speed I/O applications: "You can't just take for granted that the HSIO circuit will work to spec when you plug into a real-world circuit. Our engineers work with the customer's hardware designers to ensure that their SoC will deliver the performance they need."
SATA ATA is an evolutionary replacement for the Parallel ATA physical storage interface. The Toshiba cores are compliant with the SATA 1.0 and SATA II Gen1 i, m, and x and Gen2 i, m and x electrical specifications and support the SCSI standards. The low-power, low-cost version is optimized for 1.5Gbps (Gen1) applications while the high-performance core has been optimized for both 1.5Gbps and 3.0Gbps (Gen2) applications. The highly flexible cores were designed with many programmable operating characteristics and can be configured as either device or host. Support macrocells such as phase-locked loops (PLLs), clock generators, buffers, band gap, bias current and calibration circuits are implemented separately, allowing them to be shared in multi-channel applications to minimize die area and power consumption.
Main Features
Availability
The SATA PHY cores are currently available for customer design-in. An evaluation board is expected to be available in April 2005. Volume production is planned to start in the third quarter of 2005.
About TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, and displays for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba Corporation, one of the five largest semiconductor companies worldwide in terms of global sales for the year 2003 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com.