Frontier Design Creates IP Core for Xilinx VirtexII FPGA's
22 January, 2001 - 3GPP Log MAX Turbocoder IP Core Offers Single-chip FPGA-based Solution, Performs 7 Decoding Iterations at 40 MHz, and Offers Highest Accuracy Forward Error Correction
Frontier Design today announced that it has completed the development of a turbocoder intellectual property (IP) core for third generation WCDMA mobile base stations and handsets, based on Third Generation Partnership Program (3GPP) standards. The turbocoder core is optimized for implementation in Xilinx's Virtex II FPGAs and will be marketed exclusively by Xilinx.
Frontier Design maintains ownership of the original C-language algorithms and design of the core and is offering customization services to Xilinx customers who have specialized application requirements. Frontier also offers design services for ASIC implementation of the turbocoder core.
The 3GPP turbocoder core is used for forward error correction in third-generation WCDMA phones and base station hardware. Turbocoding is mandated as part of the 3GPP standard which requires block lengths of between 40 and 5114 bits with 2 Mbit/second data throughput, a bit error rate of 10(-6) , a 3 dB signal to noise ratio, and the capability to perform multiple iterations.
Log MAX Star Decoding Provides 0.5 dB Better SNR - Either of two different algorithms can be used for data encoding and decoding, the Log Max Star or the Max Log algorithms. Turbocoder IP cores for non-Xilinx FPGA implementation must use the less accurate Max Log algorithm because the cores are not able to achieve the required 2 Mbits/second throughput using the more computationally intensive, but more accurate, Log Max Star algorithm. Frontier Design has created a highly parallelized turbocoder IP core for Xilinx FPGAs that can execute the more accurate Log Max Star algorithm and still achieve 2 Mbits/second throughput required by the 3GPP standard. As a result, when the Xilinx turbocoder is included in a 3GPP WCDMA system, the resultant signal-to-noise ratio is at least 0.5 dB greater than that of designs incorporating competing turbocoder cores.
Single Cycle MAP Execution Provides More Iterations, Greater Accuracy
Turbocoders perform error correction by comparing two versions (called alpha and beta) of the same encoded data stream, and computing the probability that the two data streams are the same using a Maximum Aposteriori (MAP) decoder. Feeding the results of the comparison back into the MAP decoder increases the accuracy of the error correction. The more decoding iterations that are performed, the more accurate will be the error correction.
Frontier Design has created a highly parallel MAP architecture, using it's A|RT Designer EDA tool, that allows the Xilinx turbocoder core to execute each of its two MAP decoders in a single clock cycle. Each complete decoding iteration requires a total of only 2.5 cycles to complete. This is twice the throughput of competing decoders available for non-Xilinx FPGAs, which require 5 cycles for each decoding iteration. This means that, with a 40 MHz clock, the Xilinx turbocoder can perform seven or eight decoding iterations on each block, while maintaining the 2 Mbit/second required throughput. The turbocoder core offered for non-Xilinx FPGA architectures must limit itself to only 5 iterations per block so it can meet the 2 Mbits/second required throughput, with a 50 MHz clock. The higher number of decoding iterations that are possible with Xilinx's core increase the accuracy of the transmission linearly.
Alternatively, in base stations, where multiple decoders are required, the same level of accuracy could be maintained with a smaller number of FPGAs because each Xilinx FPGA could handle the decoding for more than one channel.
Eliminates External Memory Requirement
In order to compare the alpha and beta data streams, the data must be double-buffered in SRAM. The alpha metrics and additional extrinsic data must also be stored in RAM. The total memory requirement for a turbocoder with the maximum block size of 5114 bits is 41 KBytes. Since no FPGAs have this memory density on-chip an SRAM that is external to the FPGA is usually required, increasing the parts count, board size and power consumption.
Memory windowing techniques employed by Frontier Design in the architecture of the turbocoder core have reduced the total memory requirement for the Xilinx IP core to only 8 KBytes, resulting in a single chip solution in a XCV400E. This is an 80% smaller memory requirement than for the non-Xilinx solution. If external SRAM is available in the system, the turbocoder will fit in a less expensive XCV300-6.
Xilinx's turbocoder IP core is parameterizable to handle from 40 to 5114 bit blocks, to perform from one to eight iterations per block, using 7- or 8-bit words, while providing 2 Mbits/second throughput at 40 MHz, with a bit error rate of 10(-6) and a 3 dB signal to noise ratio. It requires only 2805 Virtex slices and 16 block RAMS and provides a single-chip turbocoding solution when implemented in an XCV400E.
Design Services/Cost Reduction Path Available
Frontier Design offers design services to Xilinx customers who require a customized turbocoder core for their 3G WCDMA base stations or handsets. Frontier Design's design services group will also provide Xilinx customers with highly optimized, ultra low power, custom ASIC designs of the turbocoder for use system-on-a-chip implementations.
Pricing and Availability
The Xilinx turbocoder IP core is available now to beta customers directly from Xilinx. A full production release is planned by Xilinx for the second quarter of 2001. Both the Encoder and the Decoder cores will be available over the Internet at the price of $1,800 and $18,000 respectively.
Xilinx customers who are interested in tailoring the turbocoder IP customized for their Virtex II application, or would like to investigate an ASIC cost reduction path for their design, may contact Frontier Design at email@example.com or telephone 310/540-6541 in the U.S. or +32 16 39 14 11 in Europe.
Frontier Design was founded in 1997 as the result of a management buy-out of the European Development Center of Mentor Graphics (Nasdaq:MENT). The firm's primary emphasis is its "algorithm-to-silicon" design methodology that greatly improves the creation of Silicon IP blocks starting from customer-proprietary or industry-standard algorithms in the fields of wireless telecom, consumer audio or multimedia applications. Algorithm-to-Silicon IP blocks consume less power, are less costly and require substantially less development time than other alternatives. Frontier Design sells its design services and a line of EDA tools directly from its facility in Leuven, Belgium, and from its sales office in California. Frontier Design also sells through a growing number of distributors and Value Added Resellers in Northern America, Europe, Japan and the Pacific Rim.
Frontier Design's World Wide Web site is http://www.frontierd.com. Email inquiries may be sent to firstname.lastname@example.org.