Ron Wilson, EETimes
(03/21/2005 10:00 AM EST)
System-in-package or system-on-chip? Even in designs with severe space constraints, the right level of integration is never an easy decision. SiP technology is showing a new level of maturity, nothing like the bad old days of custom-built multichip modules on unobtainium substrates. And SoC technology is extending its reach, with a number of vendors doing small-signal RF circuitry in vanilla-CMOS processes. How does the design team decide whether to put the RF stages on separate, optimized dice or to integrate them onto the baseband die?
In an interview with EE Times, Pieter Hooijmans, vice president and RF program manager at Philips, and Bill Krenik, wireless advanced-architecture manager at Texas Instruments Inc., continued a debate that began at a panel session at last year's Custom Integrated Circuits Conference.
EE Times: Gentlemen, to get right to the question, what is the best strategy for severely constrained mobile wireless devices today: SiP or SoC?
Pieter Hooijmans: Philips has chosen SiP, for a number of reasons that we believe are compelling. First, the SiP approach allows each functional block to be fabricated on the technology that serves it best. Despite the undeniable improvement in the performance of CMOS transistors, this is still important for RF circuitry, especially large-signal circuitry.
Second, having different modules on different dice permits a plug-and-play approach to a range of markets. You can do several different RF designs and use the appropriate one for each market segment, without having to change the baseband logic chip, for instance. With an SoC, you are stuck with whatever you chose to put on the die.
Third, the SiP can be much more compact in the system. Because we can integrate all the RF, including the antenna switch and power amplifier, and because we can integrate high-Q passive components, we can have a single package with an antenna signal going in and digital data coming out.
Bill Krenik: Let me start by agreeing with much of what Pieter has said. We don't differ on the advantages of SiP technology. But at TI, we believe that a careful combination of SiP and SoC technology is the best solution to these applications.
When we integrate the small-signal RF circuitry onto the baseband CMOS digital die, we see real advantages in power consumption and board area. You don't get those improvements just by pulling dice into a larger package-nor does that really reduce the cost. We still keep large-signal functions, such as the antenna switch and power amplifier, outside the SoC.
Hooijmans: So we don't disagree on the value of SiP. The discussion is over where to place the small-signal RF transceiver circuitry. I agree that putting it in CMOS is one way to save a few pennies and a few square millimeters, but it's not necessarily the best way. That decision has a major impact on system partitioning.
Krenik: And I think that in today's technology, the small-signal RF fits naturally with the digital logic. It does change the system design somewhat-after all, you are now designing an RF stage with CMOS transistors that were intended for digital. But that has benefits, too. Those transistors have an ft over 100 GHz, and you have a very fine layout pitch to work with. You can take a more aggressive approach to design than is possible in older RF processes.
In particular, if the RF-to-digital interface is internal to the chip, the baseband can share information with the RF stage at a level that wouldn't be practical with separate dice. For example, the baseband processor can be used to put the RF circuitry through a self-test process and can do on-the-fly configuration to tune the RF circuits to compensate for voltage, temperature or process variations.
Hooijmans: I agree. In fact, if you implement the RF in digital CMOS, you are forced to have more digital control over the RF stage because of the limitations in the process. But you can use the same digital techniques on a die fabricated in a true RF process, and use them to optimize performance, not to make up for process shortcomings.
But I'd like to go back to the modularity issue. As the number of wireless interfaces you are trying to support goes up, do you put them all on your SoC? How would you deal with an SoC that had 10 RF interfaces on it? The signal integrity issues, the crosstalk between the inputs, even the noise from the digital baseband would be huge issues.
Krenik: It's a major undertaking. I don't dispute that. The process engineers, packaging and test people all have to work intimately with the chip design team for something like this to work. But it is the future. Even today, in Bluetooth, for example, you have to have an SoC.
Hooijmans: Well, no. We at Philips have an SiP solution to Bluetooth that has the same size, cost and power consumption as the SoC solutions.
Krenik: OK. Let's just say that many vendors have chosen a single-chip approach in that market. That is also true for GPS receivers, and it is becoming true for wireless networks. I believe the market trend is toward SoCs. And I believe TI has solved the integration problems so that we can go there.
Hooijmans: All right, let's look at the future. In the future, we will see handset systems with multiple wireless interfaces in different combinations, and different requirements for simultaneous operation. Will you do a single giant SoC that includes all the wireless interfaces that might be needed on, say, an advanced handset? That's not the way to go. It's not a solvable problem.
Krenik: You are right that features are absolutely pouring into handsets. And each new feature brings its own antenna, its own air interface. All I'm saying is when you partition the system, put each radio with its corresponding baseband. So you end up with a cluster of SoCs; it's very modular.
By the 65-nanometer node, I believe we will see distinct segments emerging in the wireless markets, and they will have fixed combinations of functions. So we can serve each major segment with a single SoC. Then, with our experience in using SoCs in the 90-nm generation, we will be very well-positioned for a relatively easy transition.
Hooijmans: If such segments do develop, you might save a few pennies. But I think there will be few such segments where you could serve a large volume of demand with a single SoC. Remember, we will be increasing integration with the SiP approach as well, combining things where there is real architectural synergy.
Krenik: I don't agree with where you are going there. The SoC approach increases, rather than decreases, flexibility. It's more flexible because of the tighter integration you have between the functions. And if the market still wants a more modular approach for less-defined segments, we can offer that as well without changing the architecture or technology.
EET: Bill, I think you are the first person I have heard to suggest that the transition from 90 nm to 65 nm would be relatively easy.
Hooijmans: The 90- to 65-nm migration is not automatic. I will say that the more of your functionality you have in digital circuitry, the easier it becomes. But in the past, transceiver circuitry has been harder to migrate than the digital baseband. In fact, we may actually degrade RF performance overall by moving to 65 nm.
Krenik: Nothing is trivial anymore. We will have to make accommodations for 65 nm in wafer-level design and elsewhere. But because of the large number of important digital products TI has, the process engineers absolutely must make the digital migration to 65 nm easy for our designers. Then, for the RF circuitry, we are once again looking at a set of smaller, faster transistors that use less power.
EET: You have both mentioned the increasing use of digital circuitry to assist the RF. Is this being done because of integration, or is it just the best way to design RF circuitry in the current technology?
Krenik: There is definitely a trend to digitization of RF circuitry at TI. In fact, the big benefit of integration wasn't so much the combining of two dice as it was getting the RF on the die with the digital circuitry so they could work intimately. When we were doing the architectural studies for the single-chip handset, we concluded rather quickly that the best approach was to leverage digital processing power to control the analog circuits. That's not just true for integrated RF; it is equally true for separate radio chips.
Hooijmans: It's a chicken-and-egg question. You want to migrate RF circuitry to CMOS because of the high ft and low current. But if you do migrate, you find there are many drawbacks in the process that require you to do digital compensation. If you are going to do RF in CMOS, you are going to do digital correction. But in general, there are some advantages to having signals coming back to the RF stage from the baseband. For those reasons, the technique is equally valid for standalone RF chips.
EET: So employing digital technology either way, is there a difference in design feasibility between SiP and SoC approaches?
Hooijmans: With a SiP, you can use optimized technologies for each function. To be their best, the antenna switch, power amplifier and SAW filters each need their own process technology. Within that constraint, fewer dice is better. We are just talking about a slightly different partitioning.
Krenik: TI also advocates SiPs. All those other components outside the SoC are also important. But even with a SiP, it's valuable to get as much as possible onto the baseband die. Mixing all those technologies makes the SiP design more complex.
Hooijmans: Well, there's a lot of SiPs in production at Philips. I'd say it's a perfectly manageable technology.
Krenik: Perhaps. But there's a higher calling here. SiP and SoC are both essential to the evolution of the handset. We are looking at handsets in the future that have upward of a dozen radios in them for various functions. We just will not be able to do that without mastering both SiP and SoC.
EET: Finally, we come to the question of cost. If both the SiP and the SoC are well-engineered, is one approach really less expensive than the other?
Krenik: We believe the SoC will be lower in cost. It makes the handset integration simpler, it provides closer coupling between the RF and baseband circuits, and it has lower total power consumption. That last point means that, secondarily, the SoC approach may save more money in the power management circuitry. And the board area is lower.
Further, we believe the SoC will yield better than an SiP approach, and we can make the yield even better with self-test, self-correction and tuning functions that we get by the close coupling of the RF and baseband.
The learning-curve point is important. Because in the SoC the radio is largely digital, as we go along we can collect a tremendous amount of data about what is going on inside the radio. That not only means yield improvements. It also means faster debug and shorter time-to-market for our customers.
Hooijmans: These benefits of digitization also apply to the SiP, of course. I think that if both approaches are well-engineered, the difference will be marginal. But if you make a mess of something, the cost of fixing the SoC could run away with you.
Either way, clearly you have to master the technology. Recognizing that, maybe your choice of solution should be based on your control of the technologies involved as well as on your time-to-market needs.
SiP proponents cite the ability to choose the optimum process per function, while still accruing the advantages of one package.