| SAN JOSE, Calif. The sixth International Symposium on Quality Electronic Design kicked off Monday (March 21) with creators, users, and tool vendors of intellectual property airing their differences on foundry issues, process migration, and IP's role in a changing industry. |
Foundries were a target right from the opening bell. Joachim Kunkel, vice president of engineering for the DesignWare group at Synopsys, said models for analog circuits coming from the foundries were problematic, and failed to capture issues such as negative-bias temperature instability.
"It's not that they are withholding the information," Kunkel said. "It's that they don't know it. Statistical effects are only captured by collecting data from volume production. But that's far too late for IP designers, who have to be at work before the process is ready. For example, we only got good statistical models of the 130 nm process from one foundry in this last December or January. That's for 130 nm."
Naveed Sherwani, president and CEO of OpenSilicon, joined the fray with an attack on the whole idea of treadmill process migration. "What customers want is a working 130 nm process, not 90 or 65," he said. "We have probably 250 customers around the world, and we have studied maybe 400 designs with them. I can tell you that in the overwhelming majority of cases, there was no benefit to moving to 90 nm."
Sherwani continued, "Nor do I think we will see a lot of people going to 90 nm until it's at least 30 per cent cheaper than 130 nm. It isn't today And if we do stall at 130 nm for a while, that will give the other fabs—like the big ones coming on line in China—time to catch up. The capacity will drive prices down, and that will put the costs of 90 nm just that much further out of reach."
Returning to the foundry issue, Kevin MacLean, vice president of PDF Solutions, said" IP designers have to work far in advance of manufacturing. When you start developing IP for a process, volume production is so far in the future that you know the process will change before your design goes into production. IP vendors have to work with that."
"Now we are seeing another issue," MacLean said. "Foundries are refusing to share what they know about manufacturability models with others. It becomes a squeeze play to drive other providers of IP out of the market."
Sherwani replied by appearing to defend the foundries. "It is true that foundries are getting together large bodies of IP," he said. "They are doing that because they need the IP to win business. Maybe they got tired of waiting for the IP industry to mature."
Changing the negative tone was Jeff Lewis, president and CEO of analog/mixed-signal tool vendor Ciranova. "It seems to me that we are describing turmoil in the market," he said. "Turmoil is good. It will drive IP vendors to become more specialized to cope with the problems, and that will lead to better solutions."
Tets Maniwa, president of TM Associates, observed that if migration to new process nodes was slowing down, as he believed it was that might help stabilize the targets for which IP developers had to design. A similar stability, he noted, was coming from the increasing use of IP in FPGAs, which were themselves a relatively stable design target.
Ken Brock, vice president of marketing at Silvaco Data Systems, added to Maniwa's thoughts about the pressures on IP developers. "The IP business has changed dramatically in the last couple of years," he said. "It is no longer possible to design a piece of hard IP that is foundry-independent.
"IP developers got a wake-up call at 130 nm when the same IP wouldn't work in similar processes. Now, we are seeing problems not just between processes, but in lot-to-lot variations. That may be manageable in IDMs, who have developed tools for communicating what's going on from the fab back to the designers. But the foundries don't have anything like that. They are still talking in terms of SPICE models at a few process corners."
Discussing the issue of whether hard IP still had a role in the industry, Ciranova's Lewis said, "It's not either hard macros or compiled structures, it's a continuum," he said. "In most companies now, the analog designers aren't allowed to create their own polygons. They have to instantiate structures from a very carefully prepared library. The amount of methodology is increasing, but the amount of designer freedom is decreasing."
Brock added that most IP designers today had to work with models that were derived from TCAD with typical values. "But if they are pushing the edges in performance or power, they need statistical models created using Monte Carlo techniques," he said, then adding, "but designers don't understand statistics."