SAN MATEO, Calif. Licensees of the MIPS processor architecture are revving clock speeds to defend their turf against further encroachment by the PowerPC. The raft of MIPS-based introductions could herald a new push for the architecture into control-plane networking but is unlikely to win many converts among those companies that have already chosen the PowerPC path, analysts said.
On the MIPS side, SandCraft Inc. (Santa Clara, Calif.) is slated to announce in the coming week a product road map that calls for a 600-MHz chip to arrive in April, followed by devices in 2002 that will feature multiple 800-MHz processor cores.
Fellow licensees of the MIPS Technologies Inc. architecture claim to have similar plans in the making. Those companies include recent Broadcom acquisition SiByte Inc. (San Jose, Calif.) and PMC-Sierra Inc.'s MIPS Processor Division (Santa Clara), formerly Quantum Effect Design Inc. (QED).
In the opposing camp, Motorol a Inc. (Austin, Texas) this past week unveiled its latest G4 PowerPC device, the MPC7450. The announcement touted the device as the engine behind Apple Computer Inc.'s newest Macintosh computers, but Motorola executives said high-end router and switch vendors are also considering the processor.
In most cases, the chips are vying for roles as control-plane processors inside switches and routers. It's in that context that MIPS vendors are working to gain ground lost to the PowerPC late in the 1990s.
"The constellation of MIPS suppliers had some issues collectively with delivering high-performance designs. It was when QED emerged as a merchant silicon supplier that the MIPS camp at the high end started to be solidified again," said Joe Byrne, an analyst at Gartner Group Dataquest. "The intervening time was an entree for the PowerPC."
That's a plausible theory, said Mark Pittman, director of product marketing at MIPS Technologies. "We are a large community of licensees," he said. "It could be understandable that people might not know what's available."
But MIPS executives still insist their architecture is better-suited for networks than is the PowerPC. "One of the trends that, over the long run, does not work is to take the workstation [processor] core and try to jam it into an embedded device," much as Silicon Graphics Inc. attempted to do when it owned MIPS Technologies, Pittman said.
The MIPS camp took a hit when speed requirements for control processors shot up as a side-effect of increased network bandwidth. "About two years ago, no one thought you needed that much power on the control side," said Will Swearingen, director of strategic communications for Motorola's networking group.
While PowerPC clock speeds continued to rise, Dataquest's Byrne said, MIPS lost momentum: Higher-end processors "were on the road map, but they weren't coming out."
One high-profile defection was the decision by Nintendo Ltd. to use the PowerPC rather than MIPS for what would become the Gamecube console. That decision, announced in 1999, was probably made during MIPS' period of high-end doubt, Byrne said.
Large networking companies stuck with MIPS anyway, unwilling to undergo the software and hardware changes that would be required for the PowerPC, Byrne said. In particular, the Cisco IOS operating system was written for MIPS-based hardware.
But Motorola's Swearingen claimed that some OEMs were swayed by the PowerPC's consistent software platform, noting that various companies' MIPS architectures can vary. MIPS software had indeed begun to vary from one licensee to the next, but MIPS in 1998 began working to solidify the architecture, Pittman said. The MIPS32 and MIPS64 architectures include tighter specifications for software, particularly for the privileged resource architecture, which is tied closely to the operating system, he said.
The PowerPC got a further boost when startups began flooding the networking industry. With no legacy code to worry abo ut, some of them opted for PowerPC-based architectures.
Now the PowerPC is getting attention from some larger companies as they move to acquire startups. "One of the customers that we'll be disclosing [in the future] has bought three different companies that all used the PowerPC," Swearingen said.
Other large companies, Dataquest's Byrne said, have weakened in their resolve to stick with legacy code and have proved willing to take a one-time software development hit in order to shift to the PowerPC. Motorola executives claimed design wins for the architecture among some high-profile networking companies, although they would not disclose details.
Still, Byrne cautioned that the PowerPC's advantage in clock speed doesn't translate immediately into better network performance. "Probably the first criterion is power dissipation now, and that's an even harder number to grasp [than overall performance]. Power dissipation is the first or maybe the second thing they look at: 'At this power boundary, how much can you give me?' "
MIPS parts appear to retain a power-consumption advantage over the PowerPC. PMC-Sierra Inc.'s MIPS Processor Division and SiByte claim single-digit wattage, compared with the 14 W consumed by Motorola's MPC7450.
"You're going to put many, many of these chips in these machines. You've got to think about power consumption per square foot," MIPS' Pittman said. "You haven't got power to spare."
Dataquest's Byrne now sees MIPS climbing back to speed parity with the PowerPC. PMC-Sierra's QED acquisition, having completed the transition from intellectual-property provider to chip vendor, is sampling the R7000A, a 450-MHz chip. And SiByte claims to be preparing MIPS-based processors that can reach gigahertz speeds.
What the health of high-end MIPS platforms means for newcomer SandCraft remains to be seen.
The entry of "yet another high-end MIPS supplier" into the fray is either "going to help solidify the MIPS camp or it's going to split a f ixed amount of revenue among more companies," Byrne said. "That's what keeps me up at night: Is the MIPS pie getting smaller?"
The road map SandCraft will unveil the week of Jan. 15 begins with a 600-MHz, 64-bit MIPS chip called Johann I, due in April. A die shrink to 0.13-micron rules from 0.15 micron is expected to up performance to 800 MHz in the Johann II chip, being readied for third-quarter release.
SandCraft uses an 11-stage pipeline with three layers of cache memory. The pipeline is fed using speculative algorithms that SandCraft officials claim can predict upcoming instructions with 97 percent accuracy.
"It's a sophisticated pipeline in terms of both depth and parallelism," Byrne said. "On the other hand, I want to see the [EDN Embedded Microprocessor Benchmark Consortium] test scores to see how well it does performing on networking applications. It looks like there's potential for this to be among the leaders in performance, but it's always hard to tell before the product ships."
Jo hann I initially will rely on MIPS Technologies' SysAD internal bus at 133 MHz. SandCraft claims it can raise that speed to 200 MHz by switching from low-voltage differential signaling HSTL signaling, but to reach higher speeds, company officials said they will move to the Lightning Data Transport (LDT) protocol developed by Advanced Micro Devices Inc.
SandCraft isn't alone in weighing a shift from SysAD. SiByte and the new PMC-Sierra division have stated publicly that they, too, plan to move to LDT.
Moreover, PMC-Sierra division executives claim it was their idea to push SysAD to 200 MHz. "That SysAD innovation was something we've been promoting to our customers for quite a while," said Andy Keane, vice president of marketing.
MIPS executives declined to say whether the company plans to use LDT itself. But a successor to the SysAD bus, MGBLink, was included on the 20KC core and can reach aggregate throughput of 3.6 Gbytes/second, Pittman said. The interface was developed for the high-speed graphics needs of set-top boxes but could be used just as well for networking, he said.
SandCraft also added Level 3 cache, to accommodate the increased memory needs of networking. Level 3 cache is also said to be under consideration for other processor architectures, such as Intel's X86, as a way to squeeze out more processor performance.
In 2002, SandCraft plans to release Wolfgang, a chip that will include two MIPS processor cores, to be followed by Ludwig, a device based on a 1-GHz core.
Motorola, meanwhile, used this past week's MacWorld Expo to unveil its latest G4 PowerPC chip, the MPC7450, which had been described at the October 1999 Microprocessor Forum conference.
The MPC7450 is available in speed grades up to 733 MHz. The part uses a 256-kbit Level 2 cache that runs at the processor's clock speed up to 733 MHz and can support a 1- to 2-Mbyte L3 cache.