English
Design at the System Level
By Ed Sperling -- 3/25/2005
Electronic News
Electronic News sat down to discuss the future of system-level design with Vojin Zivojnovic, VP of ESL Tools at ARM; Stuart Swan, senior architect for system-level design and verification at Cadence Design Systems; Mark Milligan, VP of marketing at CoWare; and Devadas Varma, president and CEO of Calypto. What follows are excerpts of that conversation.
Click here to read more ....
Electronic News
Electronic News sat down to discuss the future of system-level design with Vojin Zivojnovic, VP of ESL Tools at ARM; Stuart Swan, senior architect for system-level design and verification at Cadence Design Systems; Mark Milligan, VP of marketing at CoWare; and Devadas Varma, president and CEO of Calypto. What follows are excerpts of that conversation.
Click here to read more ....
Related News
- USB IP Cores for the Intel Pathfinder for RISC-V Platform
- Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V
- Webinar : USB 3.1 Gen2 Device Controller IP Core usage in Intel Quartus Prime Pro
- System Level Solutions's eUSB 3.1 Gen2 Device Controller (eUSB31SF) IP core now available with Isochronous transfer support
- System Level Solutions's USB 2.0 Device Controller IP core is now available for Lattice Semiconductor FPGA platform
Breaking News
- Intel kills its RISC-V Pathfinder development kit programme
- BrainChip Tapes Out AKD1500 Chip in GlobalFoundries 22nm FD SOI Process
- 10-bit 3Msps Ultra low power SAR ADC IP core for Wireless Communication and Automotive SoCs is available for immediate licensing
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |