D&R Headline News (June 2008)

Headlines for Monday Jun. 30, 2008

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Virage Logic Acquires Impinj's Logic Non-Volatile Memory (NVM) IP Business

Virage Logic has acquired Impinj's leading solutions for logic NVM IP and added more than 50 Impinj patents to its already robust IP portfolio. In addition to the acquisition of assets, Virage Logic has hired approximately 30 former Impinj employees who were responsible for the company's logic NVM IP business.

• Altera Increases Productivity for High-Performance DSP Designs by an Order of Magnitude
• ChipX Strengthens Video and Wireless ASIC Capability With Addition of 10-Bit, 210Msps Digital to Analog Converter (DAC) Family to IP Portfolio
• CoWare Delivers Support for ARM Cortex-based Applications
• MIPS32 24Kc Pro Cores Power Magnum Semiconductor's DX1 Family of Professional Video Encoders
• ComLSI awarded second US Patent in Active VLSI Packaging (AVP) technology
• Photron Turns to Xilinx Programmable Solutions for Latest High Speed Camera
• Lattice Semiconductor Announces Automotive Versions of its Flash-Based, Non-Volatile FPGA Family
• Comsis introduce the MimoKit-MAX FPGA platform
• Hoya Purchases Moore Microprocessor Patent(TM) Portfolio License
• Tower Semiconductor to Launch Volume Production of QuickLogic's ArcticLink II VX Solution Platforms for Mobile Display Devices

Headlines for Friday Jun. 27, 2008

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GSA Reports Fabless Revenue Grew Sixteen Percent Year-over-Year, Totaling $13.4 Billion in CYQ1 2008

Fabless revenue totaled $13.4 billion, which grew 16 percent year-over-year and equated to 20 percent of the semiconductor sales total

Headlines for Thursday Jun. 26, 2008

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ARC Launches New Annual Licensing Model For Multimedia Codecs

ARC's extensive portfolio of audio, video and imaging codecs are now packaged into annually licensable libraries. This helps simplify the planning of chip companies, allowing them to better meet the constantly changing requirements of evolving consumer electronics devices.

• MOSAID Reports Fourth Quarter and Year-end Results for Fiscal 2008 and Dividend
• STMicroelectronics and NXP unveil management team for joint venture
• EVE Names Vice President of Worldwide Operations
• ADTechnology Becomes Newest Tensilica Authorized Design Center
• Cypress Incorporates Denali Blueprint for CSR Automation Management
• ProDesign CHIPit ASIC Prototyping System Accelerates Marvell ASIC Verification
• GE Fanuc Intelligent Platforms Announces First Rugged XMC Mezzanine Card To Offer Choice Of Three Xilinx Virtex-5 FPGAs

Headlines for Wednesday Jun. 25, 2008

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Mentor Graphics Delivers High-Performance Platform for the Accelerated Verification of PCI Express Applications

The platform consists of the Veloce® family of hardware-assisted verification products and the iSolveTM PCI Express product, which provides a cost-effective and efficient solution, delivering a dynamic and accurate PCI Express verification environment.

• ARM RealView Family of Tools Adds Device Support for Freescale i.MX31 Platform
• VinChip Supplies USB 2.0 Emulator to Runcom
• Sital Announces the Release of OCTAVA, a family of DDC MiniACE Compatible Devices
• DSP Group Becomes a Licensee of SPIRIT DSP Low Bitrate Voice Codec for Digital Phone Baseband Processors and SoCs
• Rambus Appoints Eric Stang to its Board of Directors
• Industry's Leading GNU-based Toolchain Available Now Optimized for MIPS Cores
• A Patented Breakthrough for all Performances of Dolphin Integration's Standard Cell Libraries

Headlines for Tuesday Jun. 24, 2008

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LG Electronics Shipping MoSys 1T-SRAM(R) DDI Technology in AMOLED-Based Mobile Phone

The MoSys 1T-SRAM Dual-Port Display macro is used as the display buffer memory mounted on the display (chip-on-glass) or on the connecting cable (chip-on-film or tape carrier package). By keeping the display buffer memory on the display itself, LG Electronics should reduce the challenges inherent in electromagnetic interference (EMI), while cutting overall display power consumption.

• Atmel Announces ARM Cortex-M3 License and AT91SAM3 Flash MCU Family
• Agility Introduces Programmable Platform for Image and Signal Processing
• Phylinks further strengthens team with new CEO, additional director
• Nokia to acquire Symbian Limited to enable evolution of the leading open mobile platform
• Open-Silicon Adopts Broad Range of MIPS(R) Cores to Speed Time-to-market for Next-generation ASIC Designs
• IP vendor Sonics scraps IPO
• Veriest Verification (Israel) announces close collaboration with HDL Design House (Serbia)
• Sigma Designs Announces CoAir, the World's First Ultrawideband Chipset With Integrated Wireless, Coax and Gigabit Ethernet for High Speed Whole Home Networking

Headlines for Monday Jun. 23, 2008

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Semiconductor IP market grew 8% in 2007, says Gartner

The growth of the worldwide market for semiconductor intellectual property slipped back to a single-digit percentage in 2007, reflecting signs of maturity, less organic growth and more growth by acquisition, according to market research company Gartner.

• Actel Expands Processor Ecosystem for Low-Power FPGAs
• Tower Semiconductor Chosen as Strategic Supplier for a Select Portfolio of CMOS Products by ON Semiconductor
• Lattice Enhances its Wireless Base Station Solutions Portfolio
• Jennic first to introduce 32-bit ZigBee PRO wireless microcontroller
• Frontier Silicon announces unified multi-region digital radio receiver

Headlines for Friday Jun. 20, 2008

• Wi-LAN Initiates Litigation Against Motorola, RIM and UTStarCom / Company confirms settlement of Marvell Dispute
• Wi-LAN Provides Mid-Quarter Update on Licensing Activities

Headlines for Thursday Jun. 19, 2008

Top Story

Commentary: Cadence-Mentor: facts vs. emotions

History will be the final judge of Michael J. Fister's decision to make a hostile bid for Mentor Graphics Inc.

• Patriot Scientific Announces Agreement with NuPOWER Semiconductor to License Power Management IP Portfolio
• RF Engines sign further contract with Thales UK
• Cadence-Mentor deal makes sense, says analyst

Headlines for Wednesday Jun. 18, 2008

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Synopsys' DesignWare Verification IP Enhanced to Support New SATA 6Gbps Specification

The DesignWare Verification IP supports all major simulators and verification languages including Verilog, SystemVerilog, VHDL and Vera, allowing designers to quickly and efficiently create a comprehensive SATA- based environment. In addition, the Verification IP for SATA delivers up to 5X performance improvement when used with Synopsys' VCS® simulation tool

• ARM7-Based MCU With FPGA Interface to Multi-Layer AHB
• Ashling Microsystems New range of Development tools for ARM powered devices
• XtremeData Begins Shipping 1066 MHz Altera Stratix III FPGA-Based Intel FSB Module
• Analogix Sues Silicon Image, Inc. for Antitrust Violations

Headlines for Tuesday Jun. 17, 2008

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Cadence Proposes to Acquire Mentor Graphics for $16.00 per Share in Cash

The transaction price represents a total enterprise value of $1.6 billion on a fully diluted basis, which reflects Mentor Graphics' net debt of $69 million.

• Analyst: Cadence/Mentor merger "a bad idea"
• Mentor Graphics Responds to Proposal from Cadence Design Systems
• Kaben Wireless Silicon releases high-performance frequency synthesizer for WiMAX applications
• Mentor Graphics Delivers High-Performance Platform for the Accelerated Verification of Multimedia Applications
• On2 Joins MIPS Alliance Program; Leading Video Codec Solutions Now Available for MIPS-Based Processors
• Samsung Sues Polaroid and Westinghouse for ATSC Patent Infringement
• Letter to Shareholders from Patriot Scientific President/CEO Rick Goerner
• CPU Tech Wins $47M Delivery Order for Acalis(R)-Based Electronics

Headlines for Monday Jun. 16, 2008

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Virage Logic Unveils One Mega-Bit Embedded Reprogrammable Non-Volatile Memory (NVM) on Standard CMOS Process

Combining user-defined functionality with Virage Logic’s high-capacity read-only memory (ROM) and NOVeA® Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up to 16 Megabits of code storage and is manufactured on industry standard CMOS processes with no additional mask or process steps.

• Silicon Image Responds to Analogix Semiconductor Lawsuit
• XStreamHD Licenses and Deploys CEVA Enterprise SATA IP in XStreamHD HD Media Server
• IP Cores, Inc. Shipped Ultracompact AES and AES/GCM IP Cores for Actel FPGA Supporting FIPS-197, IEEE 802.1AE MACsec and P1619.1 Standards
• Silvus Technologies and Fastrack Design Form Partnership to Benefit System-on-Chip Companies
• Eureka Technology Lowers the Cost of Secure Digital (SD) and MultiMedia Card (MMC) Development
• Lattice Semiconductor Appoints New President And Chief Executive Officer
• Virtutech Announces Breakthrough Hybrid Simulation Capability Allowing Mixed Levels of Model Abstraction
• Cadence Enhances RF Verification With High-Performance 'Turbo' Technology and Comprehensive Electromagnetic Analysis
• Eight-core microprocessor from Freescale redefines state-of-the-art for embedded multicore processing

Headlines for Friday Jun. 13, 2008

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eInfochips announces AVM 3.0 & OVM Compliant SystemVerilog AMBA AHB Verification IP

Integration of AMBA AHB AVM 3.0 Ensures Availability of OVM Compliant High-Quality Verification IP for Advanced SystemVerilog Verification

• Automotive FPGAs make grade
• Actel Confirms Second Quarter Guidance and Adds One Million Shares to its Stock Repurchase Program
• Mentor Graphics Expands Nucleus Platform Solutions to Freescale i.MX31 Processor for Multimedia Applications

Headlines for Thursday Jun. 12, 2008

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Faraday Announces the First Commercially Available 1GHz Memory Compiler to Enable GHz CPU & SoC Designs in UMC 90nm

The single-port memory compiler utilizes advanced layout and circuit design techniques to provide up to 1GHz speed and keeps the same power and area requirement as generic memory solutions.

• Radiocomp & Altera partner on OBSAI/CPRI cores
• austriamicrosystems further expands field-programmable OTP memory portfolio for its advanced 0.35um process family
• Imperas Announces Licensing, Distribution Relationship with Tensilica
• Enhanced Zatara(TM) ARM(R)-Based ASSP From Zilog Adds Integrated Security Features, On-Chip USB for Reduced BOM Costs and Faster Time-to-Market

Headlines for Wednesday Jun. 11, 2008

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Synopsys Announces DesignWare IP for PCI Express with PCI-SIG I/O Virtualization Technology

The PCI-SIG I/O Virtualization (IOV) technology, which builds on the PCI Express (PCIe) protocol stack, reduces the system hardware requirements by enabling the simultaneous sharing of peripherals across multiple CPUs or operating systems.

• Tiempo announces a fully-asynchronous delay insensitive DES crypto-processor chip
• GDA Demonstrates its PCI-Express Gen 2 Controller (GPEX-GEN2) at 5Gbps for High Performance Applications
• Magillem and Sonics Announce Joint Donation of IP-XACT Support of OCP Protocols to the OCP-International Partnership
• Sonic Focus Featured in HP's New "TouchSmart" PC
• UMC tips roadmap, questions 450-mm

Headlines for Tuesday Jun. 10, 2008

Top Story

Video: Virage's McCranie says IP is alive and well

At DAC, Mark LaPedus, semiconductor editor from EE Times, caught up with Daniel McCranie, president, chief executive and chairman of Virage Logic Corp. In a video, McCranie talks about the outlook, challenges and trends in intellectual property (IP).

• NationalChip Licenses ARM CPU for Next-generation STB Chipset Designs
• The truth about last year's Xbox 360 recall
• PCI-SIG Completes I/O Virtualization Suite of Specifications
• Synopsys' Synplicity Business Group Announces New Products and Product Enhancements Providing Designers With a Faster Path to Silicon
• TSMC May 2008 Sales Report
• SafeNet Announces World's First Complete MACsec Embedded Security Solutions for LAN and Metro Ethernet Communications
• Athena Wins Army Contract for Anti-Tamper Technology
• COMAG Sued for Infringement of MPEG-2 Patents
• Target Compiler Technologies Announces Key Design Wins and New Positioning

Headlines for Monday Jun. 09, 2008

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Freescale and Altera Partner to Deliver World's First Soft ColdFire(R) Cores on FPGAs

Popular V1 Core Available at No Charge Through IPextreme for Altera's Cyclone(R) III FPGA; SOPC Builder-Ready Component Backed by Broad Ecosystem

• Cadence Delivers OVM-Compliant Verification IP
• Altera SOPC Builder Tool Extends System-Level Design Lead With Third Embedded Soft Processor Option
• Synopsys Delivers 45-Nanometer Low Power Reference Flow for Common Platform Technology Validated with ARM Physical IP
• DesignArt Networks Unveils 4G Silicon Platform and Delivers Fully Integrated WiMAX SoC
• Lattice Expands Wireless Solutions with 3GPP-LTE CTC Decoder IP Core
• IPextreme® Brings ColdFire® Architecture to the FPGA Masses
• TSMC Unified DFM Architecture Promises Improved Yields and Accelerated Time-to-Market
• Chartered Invests in Design Services Firm
• Open SystemC Initiative Announces Completion of New Standard Enabling the Real-World Interoperability of Transaction-Level Models
• Synopsys and UMC Release 65-Nanometer Low Power Design Flow Enabled by the Unified Power Format
• Cadence Collaborates with UMC to Deliver 65nm CPF-Based Low-Power Reference Design Flow
• Cadence Collaborates With Common Platform and Arm to Deliver 45-NM RTL-to-GDSII Reference Flow
• STMicroelectronics Announces Certified Design Flow to Accelerate Creation of Next-Generation Silicon
• Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm

Headlines for Friday Jun. 06, 2008

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Duolog Technologies Pioneers I/O Fabric Generator for Complex SoC Designs

Duolog Technologies announced its new Spinner™ I/O fabric generation tool for automated, bug-free I/O fabric synthesis of complex SoCs.

• ARM Releases AAC, MP3, MPEG-4, H.264 and FFT OpenMAX DL Libraries, Highly Optimized for Cortex-A8/NEON and ARM11 Processors
• Noesis Technologies releases 10Gbps AWGN channel emulator IP
• FS2 Introduces System Navigator Probe for Development Using the New Ultra Low Power Handshake Solutions Memory Extension HT80C51 Core
• IPextreme Names Semiconductor Industry Veteran Rick Tomihiro as Vice President of Marketing
• HDL Design House has a new representative for Western Europe
• Faraday Monthly Sales Report - May 2008

Headlines for Thursday Jun. 05, 2008

Top Story

Imagination Technologies Extends Low-Power Receiver IP Platform

Imagination Technologies announced today that it has added NorDig-Unified 1.0.3.compliant DVB-T to its licensable receiver IP platform family.

• Innovaide Releases Licensable Packet Processing and Traffic Management IP
• Arasan Chip Systems PCI Express Gen2 Solution Named to PCI-SIG Integrators List
• ARM Powered NVIDIA Tegra Packs More Punch - Video Comparison with Intel
• Evatronix enhances its Ethernet MAC product line with MAC-1G PCS IP core
• Texas Instruments Adopts Sonics SMART Interconnect(TM) Solutions for OMAP(TM) 3430 Application Processor
• MOSAID Signs Patent License Agreement With Fabless Semiconductor Memory Company
• Zoran Corporation Adds Frame Rate Conversion Technology Through Acquisition of Let It Wave
• eASIC Appoints Matthew R. Ready as Senior Vice President of Worldwide Sales
• Certicom Reports Year-end Results for Fiscal 2008
• Onespin Announces Industry's First SVA Solution for Gap-Free Verification
• Certess Announces Toshiba's Deployment of its Functional Qualification Solution
• Berkeley Design Automation Enters Analog/RF Mixed-Signal Verification

Headlines for Wednesday Jun. 04, 2008

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SoC Solutions Builds FPGA System in Record Time Using Synopsys' ReadyIP Flow and CAST IP Cores

CAST and SoC Solutions recently proved the effectiveness of a new FPGA design capability from Synopsys’ Synplicity Business Group by developing a complete 32-bit processor-based system in just three and a half days.

• Bluespec's High-Level Synthesis Toolset is Selected by Mercury Computer Systems for Creation of Next Generation Advanced Computing IP
• Globetech Solutions' Verification IP for Latest IEEE Test and Debug Standard Selected by STMicroelectronics
• Sarnoff Expands License in ESD Solution for Toshiba
• Xilinx Completes Functional Reorganization
• CEVA and ARM Partner to Enhance Development Support of CEVA DSP + ARM Multiprocessor SoCs
• Enea and CEVA Announce Enea OSE ck Real-Time Operating System for CEVA-X and CEVA-TeakLite-III DSP Architectures
• MindTree Unveils Bluetooth Automotive SDK
• Synopsys Delivers Comprehensive Design Support for TSMC 40-Nanometer Process
• Tensilica and SPIRIT DSP Form Strategic Partnership and Deliver Mobile Multimedia Audio and Voice for Xtensa HiFi 2 Audio Engine
• Wi-LAN Reports Second Quarter 2008 Financial Results

Headlines for Tuesday Jun. 03, 2008

Top Story

New TSMC Reference Flow 9.0 Supports 40nm Process Technology

TSMC today introduced Reference Flow 9.0, the latest version of TSMC’s industry-leading design methodology to lower design obstacles, improve design margins, and increase yields of its 40nm process technology.

• Freescale Delivers Virtual Platforms to Continental Using CoWare ESL 2.0 Solutions
• Altera Updates Second Quarter Guidance
• DAFCA and Denali Software Announce Collaboration to Expand FlashPoint Platform Integration Features
• Tundra Semiconductor Terminates Product Acquisition and License Agreements with IBM
• CSR launches the world's most highly integrated wireless single chip
• ARM, Renesas Technology and Synopsys Define Industry's First Low-Power Verification Methodology
• Arithmatica's Datapath Synthesis Used by Solarflare Communications for New 10GBASE-T PHY Design
• Virage Logic Supports TSMC's Power Trim Service(TM) for Advanced Process Nodes
• Broadcom Announces Groundbreaking 65 Nanometer Single-Chip Bluetooth 2.1 + EDR Solution for Mobile Handsets
• ARC Announces Partnership with ViXS Systems
• Themis Builds Blade Server Based on Sun Microsystems' UltraSPARC T2 Processor
• Dongbu HiTek Launches Industry's First 0.18-micron BCDMOS Process
• EVE Appoints Koji Iwagami General Manager of EVE K.K.

Headlines for Monday Jun. 02, 2008

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ARM Mali-400 MP Technology Brings High-end Graphics to all Consumer Devices

ARM today announced the ARM® Mali™-400 MP scalable multiprocessor graphics solution, capable of delivering performance of up to 1G pixels per second and enabling licensees to serve multiple product markets with the same architecture, whilst retaining the flexibility to choose the optimum power, performance and area configuration for their application.

• eASIC zooms past 100th
• ChipX Introduces Synthesizable 32-Bit CPU With Best-in-Class Code Density for Embedded and Consumer Applications
• SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications
• ARM Multiprocessing Technology Powers Ground Breaking NVIDIA Tegra Mobile Computer-on-a-Chip
• Tensilica Announces New Open Source Linux Emphasis, Broadens Processor Core Ecosystem with New Linux Partners TimeSys and Embedded Alley
• Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem
• Timesys Announces Strategic Alliance with Tensilica
• Embedded Alley Adds Embedded Linux Support for Tensilica's Processor Cores
• Avery Design Realizes Insight For Formal Bug Hunting and Coverage Closure