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Thalia's AMALIA Technology Analyzer de-risks Analog IP reuse for major IP houses and IC manufacturers (Tuesday May. 18, 2021)
Thalia Design Automation, an IP reuse company and experts in the development and deployment of automation solutions for Analog & Mixed Signal IP Reuse, today announced further upgrades and enhancements to its Technology Analyzer.
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Riviera-PRO Enables VHDL-2019 Users to Unleash the Power of the Language's New Additions (Tuesday May. 18, 2021)
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, provides industry’s most comprehensive implementation of VHDL 2019 for both Windows and Linux platforms with the latest release of Riviera-PRO (release version 2021.04).
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Xpeedic On-Chip Passive EM Simulation Suite Certified for Samsung Foundry 8LPP Process Technology (Monday May. 17, 2021)
Xpeedic today announced that its on-chip passive EM simulation suite has been certified by Samsung Foundry for its advanced 8LPP (8nm Low Power Plus) process technology.
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Synopsys Extends Verification Hardware Market Leadership with Breakthrough Emulation Performance (Thursday May. 13, 2021)
Synopsys, Inc. (Nasdaq: SNPS) today announced disruptive innovations in emulation delivering 10 MHz performance to speed hardware and software verification of complex system-on-chips (SoCs) in areas such as high-performance computing (HPC), 5G, GPU, artificial intelligence (AI) and automotive.
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Real Intent Expands ISO 26262 Functional Safety Compliance for Static Sign-Off Products (Wednesday May. 12, 2021)
Real Intent, Inc., today announced that the following static sign-off tools — Meridian RDC (Reset Domain Crossing), Meridian CDC (Clock Domain Crossing), Verix Multimode CDC, Ascent Lint (RTL & Netlist Linting), Ascent AutoFormal, Verix DFT, and iDebug (debug environment) — are now certified for use in ISO 26262 functional safety compliant flows.
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Synopsys ZeBu Server 4 Adopted by Xsight Labs for Intelligent Networking Switch Processor (Monday May. 10, 2021)
ZeBu Server 4's performance and 7 billion gate cloud capacity has enabled Xsight Labs to further strengthen its pre-tapeout validation methodology using complex networking workloads with full system-on-chip (SoC) emulation.
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Synopsys Delivers Enhanced Memory Design Productivity to Nanya Technology (Wednesday May. 05, 2021)
Nanya Selects Synopsys Custom Design Platform to Accelerate Design of Next-Generation Memories for Mobile, Automotive, Consumer and Industrial Markets
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SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio (Tuesday May. 04, 2021)
SmartDV™ Technologies, the leader in Design and Verification Intellectual Property (IP), today unveiled a tool suite that automates the protocol debugging process and testbench creation by eliminating tedious and error-prone manual approaches and improving productivity.
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Global Unichip Corporation Deploys Cadence Clarity 3D Solver to Achieve 5X Speedup of Systems Analysis for 112G Long-Reach Network Switch (Thursday Apr. 29, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Global Unichip Corporation (GUC) successfully deployed the Cadence® Clarity™ 3D Solver in its simulation workflow to design a complex network switch with hundreds of 112G PAM4 long-reach (LR) lanes.
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Arm Leverages Synopsys Fusion Compiler to Enable Best PPA for Latest Neoverse Platforms (Wednesday Apr. 28, 2021)
Synopsys today announced that Fusion Compiler™, the industry's only single data model and golden signoff-enabled RTL-to-GDSll implementation solution, has been deployed by Arm to enable optimal power, performance and area (PPA) on next-generation Arm® Neoverse™ V1 and N2 infrastructure cores.
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Synopsys and Arm Deliver Comprehensive Solutions to Increase Performance and Accelerate Time-to-Market for High-Performance Computing, Data Center and AI SoCs (Tuesday Apr. 27, 2021)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Arm and Synopsys have expanded their strategic collaboration to deliver optimized design, verification, silicon IP, software security, quality solutions and reference flows for Arm®-based system-on chips (SoCs), including the Arm Neoverse™ V1 and N2 platforms.
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Defacto Technologies Announces SoC Compiler, v9 (Monday Apr. 26, 2021)
Defacto Technologies today announces v9 of their EDA software offering, SoC Compiler, replacing the STAR product name.
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Synopsys Introduces PrimeLib Unified Library Characterization and Validation Solution for Accelerated Access to Advanced Process Nodes (Wednesday Apr. 21, 2021)
Golden Signoff Accuracy Coupled with 10X Cloud-optimized Performance Speeds Turnaround Time and Reduces Hardware Costs
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Synopsys Unleashes PrimeSim Continuum Solution to Accelerate the Design of Hyper-Convergent ICs for Memory, AI, Automotive and 5G Applications (Tuesday Apr. 20, 2021)
PrimeSim Continuum, a foundation of the Synopsys Custom Design Platform, is built on next-generation SPICE and FastSPICE architectures and is the industry's only proven GPU acceleration technology providing design teams 10X runtime improvements with golden signoff accuracy.
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TSMC certifies Aprisa place-and-route solution from Siemens on TSMC's N6 process (Tuesday Apr. 20, 2021)
Siemens today announced that its close collaboration with longtime foundry partner TSMC has resulted in the certification of its Aprisa place-and-route solution for TSMC’s advanced N6 process, a powerful enhancement of the broadly-adopted 7-nanometer (nm) family of technologies.
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Cadence Pegasus Verification System Certified for Samsung Foundry 5nm and 7nm Process Technologies (Monday Apr. 19, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® Pegasus™ Verification System has achieved certification for Samsung Foundry’s 5nm and 7nm process technologies.
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Synopsys AI-Driven Design System Enables Renesas to Achieve Breakthrough in Productivity (Thursday Apr. 15, 2021)
Synopsys today announced the adoption of DSO.ai™ (Design Space Optimization AI), Synopsys' award-winning autonomous artificial intelligence (AI) design system, by Renesas into its advanced automotive chip design environment.
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S2C Announces Next-Gen Prodigy MDM Pro to Simplify and Speed Up FPGA Prototyping Debug Process (Thursday Apr. 15, 2021)
S2C’s popular Prodigy Multi-Debug Module (MDMTM) has been helping FPGA prototyping customers to shorten the debug process and get their designs to market quickly with greater confidence.
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HDL Design House selects Silicon Frontline's P2P Software for Fast, Easy IR Drop and Resistance Mapping (Friday Apr. 09, 2021)
Silicon Frontline Technology today announced that HDL Design House, a leading-edge digital, analog, and back-end design and verification services provider, has selected the company’s P2P (IR Drop and Resistance Mapping) for fast, early IR Drop analysis and full-chip verification of their CMOS image sensors.
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Cadence Collaborates with Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm (Friday Apr. 09, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has optimized the Cadence® digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm.
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Cadence Delivers Automotive Reference Flow for Samsung Foundry 14LPU Process Technology (Friday Apr. 09, 2021)
Cadence today announced the availability of an automotive-optimized Cadence® digital full flow for Samsung Foundry’s 14LPU process technology. The Cadence flow was demonstrated using the high-performance, low-power Cadence Tensilica® ConnX B10 digital signal processor (DSP) for automotive radar, lidar and vehicle-to-everything (V2X) applications.
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Synopsys and Samsung Foundry Collaboration Delivers High-Performance Physical Signoff on Samsung SAFE Cloud Design Platform (Tuesday Apr. 06, 2021)
Synopsys, Inc. (Nasdaq: SNPS) today announced that its IC Validator physical verification solution has been deployed on Samsung's SAFE Cloud Design Platform (SAFE-CDP). This collaboration enables designers targeting Samsung Foundry advanced process nodes to achieve significant compute resource savings of up to 30 percent and faster signoff.
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Siemens introduces PCBflow, a secure, cloud-based solution for accelerating design-to-manufacturing handoff for printed circuit boards (Tuesday Apr. 06, 2021)
PCBflow extends Siemens’ Xcelerator™ portfolio with a secure environment for printed circuit board (PCB) design teams to interact with a variety of manufacturers, and by rapidly performing a range of design-for-manufacturing (DFM) analyses in the context of each manufacturers’ process capabilities, which helps customers accelerate design-to-production handoff.
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Synopsys Extends Market Leadership in Verification Hardware with Performance and Enterprise Scalability Innovations (Monday Apr. 05, 2021)
HAPS-100 Delivers 2x Higher Prototype Performance and 4x Higher Debug Performance for Software and Hardware Verification of Complex SoCs
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Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre Silicon Hardware Debug and Software Validation (Monday Apr. 05, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence® Palladium® Z2 Enterprise Emulation and Protium™ X2 Enterprise Prototyping systems to handle the exponentially increasing system design complexity and time-to-market pressures.
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GUC Enlists AWS Partner proteanTecs to Increase ASIC Reliability and Quality at Scale (Monday Mar. 29, 2021)
Global Unichip Corporation (GUC) helps system and semiconductor companies develop application-specific integrated circuits (ASICs), or microchips. Each generation of ASICs has a more complex design and uses more advanced semiconductor processes, making it harder to reach quality targets.
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Siemens delivers next-generation, comprehensive hardware-assisted verification system (Friday Mar. 26, 2021)
Siemens Digital Industries Software today unveiled its next-generation Veloce™ hardware-assisted verification system for the rapid verification of highly sophisticated, next-generation integrated circuit (IC) designs.
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GUC and Ansys Expedite Advanced-IC Designs for Next-Generation Applications with State-of-the-Art Simulation Workflow (Friday Mar. 26, 2021)
The workflow enables enhanced innovation across CoWoS, InFO and interposer designs, including GUC’s newly announced, silicon-proven GUC multi-die interLink (GLink) interface, which is essential for developing leading-edge AI, HPC and data center networking applications.
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Synopsys Collaborates with Keysight Technologies to Deliver Integrated Custom Design Flow for 5G Designs (Wednesday Mar. 24, 2021)
Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with Keysight Technologies to seamlessly integrate Keysight's RFPro solution with Synopsys's Custom Compiler™ solution, enabling mutual customers to create 5G system-on-chip (SoC) designs.
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GLOBALFOUNDRIES and Cadence Add Machine Learning Capabilities to DFM Signoff for GF's Most Advanced FinFET Solutions (Wednesday Mar. 24, 2021)
GLOBALFOUNDRIES® (GF®), the world’s leading specialty foundry, and Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a collaboration to facilitate design for manufacturing (DFM) signoff with machine learning (ML) prediction capabilities.