Ultra low-power 2.4 GHz transceiver for Bluetooth Low Energy 5
Xylon announces Motion JPEG Encoder
January 29, 2018, Zagreb (Croatia) – Xylon announces the logiJPGE Motion JPEG Encoder IP core compliant to the ISO/IEC 10928-1 baseline DCT JPEG standard and optimized for Xilinx® Zynq®-7000 All Programmable SoC and FPGA devices. This IP core can be paired with Xylon's logiJPGD Multi-Channel MJPEG Decoder IP core, or used with third-party decoder counterparts in a wide variety of applications.
The logiJPGE decreases the data throughput required for the video transport. For example, in the FullHD (1920x1080@60) resolution video camera, the required bandwidth of 2400 Mbps can be decreased to 100 Mbps that is easily managable through an ordinary Ethernet connection.
The logiJPGE Motion JPEG Encoder IP core is fully embedded into Xilinx Vivado® Design Suite to hide a complexity from the end-user and to make its integration with the on-chip AMBA AXI4 bus easy. The logiJPGE reference design, which is on request available from Xylon, can be used as a starting point to evaluate and develop Xilinx-based MJPEG video processing embedded systems. Please submit your request for evaluation at info@logicbricks.com.
Get the logiJPGE MJPEG Encoder IP core's datasheet from: http://www.logicbricks.com/Documentation/Datasheets/IP/logiJPGE_hds.pdf
Get the logiJPGD Multi-Channel MJPEG Decoder IP core's datasheet: https://www.logicbricks.com/Documentation/Datasheets/IP/logiJPGD_hds.pdf
Key features:
• Supports Xilinx® Zynq®-7000 All Programmable SoC and 7 series FPGA families
• Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
• On-the-Fly video encoding to Motion JPEG stream
• Configurable video compression factor
• Video input/output resolutions up to 2048x2048
• Supported pixel formats: YUV 4:2:0 and YUV 4:2:2
• ARM® AMBA® AXI4-Stream compliang video input and video output
• Available IP core deliverables for Xilinx Vivado® Design Suite
• IP deliverables include documentation and technical support
• Reference design available on request
|
Xylon Hot IP
Related News
- 4i2i Announces Motion JPEG VHDL Encoder and Decoder Core
- Xylon reveals new lossless MJPEG Encoder and Decoder IP Cores
- intoPIX Releases a New Range of Compact Encoders and Decoders for JPEG XS
- Alma Technologies Announces Availability of a New Ultra-High Throughput JPEG 2000 Encoder IP Core
- CAST Expands Streaming Video IP Line with Motion JPEG Subsystem
Breaking News
- Alphawave Semi announced today a refocussing of the Board of Directors after reaching the three-year milestone since the Company's IPO
- Synopsys and Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU with Leading Performance on Samsung Foundry's GAA Process
- Worldwide Silicon Wafer Shipments Dip 5% in Q1 2024, SEMI Reports
- GOWIN's progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment
- PCI-SIG® Announces CopprLink™ Cable Specifications for PCIe® 5.0 and 6.0 Technology
Most Popular
- Silvaco Announces Launch of Initial Public Offering
- TSMC's A16 Process Moves Goalposts in Tech-Leadership Game
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- QuickLogic Releases Aurora 2.6 with Expanded Operating System Support and Up to 15% Faster Performance
E-mail This Article | Printer-Friendly Page |