soft eFPGA IP
TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
UMC, eMemory, and PUFsecurity Announce Successful Silicon-Proven Secure Embedded Flash IP
Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller
Vayyar Selects proteanTecs to Advance Vehicle Safety with Predictive Analytics
Implementing C model integration using DPI in SystemVerilog
Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
Lossless Compression Efficiency of JPEG-LS, PNG, QOI and JPEG2000: A Comparative Study
The design of the NoC is key to the success of large, high-performance compute SoCs
TSMC FINFLEX - Ultimate Performance, Power Efficiency, Density and Flexibility
Introducing Open Access: SoC design for everyone
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