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GigaDevice partners with SEGGER on Embedded Studio for RISC-V	Dec. 14, 2023

SEGGER adds Stack Overflow Prevention (STOP) technology to Embedded Studio for ARM	Jun. 19, 2023

SEGGER introduces streaming trace probe for SiFive RISC-V cores	Oct. 25, 2022

SEGGER and Cadence team up to add native J-Link support for Cadence Tensilica cores	Oct. 04, 2022

SEGGER licenses C++ runtime library to SiFive for code size and performance efficiency	Sep. 29, 2022

SEGGER's product line fully supports Arm Cortex-M85	Jul. 04, 2022

SEGGER and Renesas deliver Device Lifecycle Management (DLM) for RA MCUs	Apr. 14, 2022

SEGGER Embedded Studio for Arm now with hard real-time C++ support	Mar. 31, 2022

SEGGER releases new Embedded Studio for RISC-V with hard real-time C++ support	Mar. 17, 2022

SEGGER announces that Renesas has licensed emWin for all RX microcontrollers	Mar. 14, 2022

SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost	Mar. 10, 2022

SEGGER adds 64-bit RISC-V support to Embedded Studio	Dec. 09, 2021

Haawking licenses SEGGER's emRun for RISC-V	Aug. 31, 2021

SEGGER's emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements	May. 31, 2021

SEGGER introduces new Open Flashloader for direct programming of any RISC-V system	Jan. 12, 2021

RISC-V embedded variant RV32E now fully supported by SEGGER's Floating-Point library	Sep. 21, 2020

SEGGER announces comprehensive support for SiFive Insight debug/trace platform	Apr. 01, 2020

SEGGER releases Floating-Point Library for RISC-V	Feb. 10, 2020

SEGGER presents RTOS, stacks, middleware for RISC-V	Dec. 11, 2017

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