 |
Programs seeks to boost over-the-Web core evaluation
By Peter Clarke, EE Times
March 28, 2000 (2:46 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000328S0046
LONDON — Simutech LLC will launch an industry partnership this week to investigate the remote evaluation of intellectual property cores over the Internet using Rave, its prototyping hardware system. Simutech said the partnership, to get under way at the Design Automation and Test Europe (Date) 2000 conference in Paris, will seek to establish a secure, accurate and high-performance way to evaluate both hardware and software intellectual property (IP). Members will guide the evolution of the Simutech platform and use models to create an IP delivery and evaluation system that meets a range of requirements and IP configurations. Founding members of the partnership — the Intellectual Property Evaluation Partners Program (IPEP) — include ARC Cores, Cadence, DSP Group, Design and Reuse, Dolphin Integration, Infineon Technologies, InSilicon, Integrated Silicon Systems (ISS), PalmChip, the Alba Center, Sican, Sonics, TechOnLine and Quicktu rn Design. Simutech (Vancouver, Wash.) is also working with the Alba Center (Livingston, Scotland) to run a pilot project on Rave prototyping over the Internet and is providing Design and Reuse (Grenoble, France) with a Rave unit to encourage the development of third-party services based on Rave core prototyping and evaluation. Simutech said Rave, a hardware-assisted verification tool, runs 10,000 times faster than software simulation and 10 times faster than other emulation systems. It consists of a cabinet loaded with up to 31 CoreBoards, each of which contains one or more IP blocks implemented as a high-density FPGA or as a bonded-out core. CoreBoards are linked through a 128-bit backplane bus. The user controls the verification through a PC or Unix workstation. Users can also run Rave with an HDL simulator. Last November at the IP99 Europe exhibition and conference, Simutech and ISS demonstrated the remote evaluation of a Viterbi decoder block implemented in silicon, over the Internet using Rave. Simutech seeks to accelerate that potential at Date with the partner program. According to Simutech, Rave will allow design groups to try cores in silicon prior to licensing. The ability to do this from a remote site could unblock a bottleneck preventing effective IP reuse, e-commerce and system-on-chip development. "There are a lot of issues over access security, parameterized IP, secure and third-party sites as well as the issues of Internet bandwidth," said Steve Glaser, vice president of marketing for Simutech. "We need the IPEP to provide guidance to support the usage models they require." Glaser said that partners could share experiences and requirements via e-mail, although private discussions with Simutech will also be possible. Partners had committed to making at least some of their IP cores available on CoreBoards. The Rave prototyping unit will build up a library of cores to help with evaluations between processor or DSP cores and peripherals. Reconfigurability's the thing Alex Bedarida, senior director of DSP cores at Infineon Technologies AG, said, "Simutech's approach to rapid prototyping will allow integrators of complex systems-on-chip based on our Carmel DSP core to develop and test their software while they tape out their silicon. Today the name of the game is reconfigurability. The reconfigurability of Simutech's Rave systems amplifies the benefits of the configurable long-instruction-word technology that is the foundation of the Carmel DSP." The Alba Center will tackle geographically remote IP evaluation in a one-year Rave-based pilot project. The project is intended to define the usage model and methodology employed to evaluate IP blocks over the Internet. The Rave unit will be housed at the Livingston-based Institute for System Level Integration.