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Intel finds allies for futuristic nonvolatile memory
By Anthony Cataldo, EE Times
November 13, 2001 (6:39 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011113S0073
SAN MATEO, Calif. — Intel Corp. has recruited nonvolatile memory design specialist Azalea Microelectronics Corp. to build a prototype 4-Mbit ovonic unified memory, which some consider a potential successor to flash memory. Within the next three months, Intel is scheduled to present two technical papers that will describe the basic cell structure and fabrication method as well as a test chip based on OUM, which stores bits by generating different levels of low and high resistance on a glassy material. Intel has enlisted Azalea (Santa Clara, Calif.) to design the 4-Mbit test chip. "We're so busy with our own designs that we decided not to make this an internal effort. So we looked around at nonvolatile memory designers to do the test chip design," said Stefan Lai, vice president of Intel's technology and manufacturing group. The test chip will be a 0.18-micron, 3-volt CMOS design. It is said to have direct overwrite capability, so the cel ls do not have to be erased before they are programmed. The chip can endure 1012 cycles, and can retain data for 10 years at 120°C. The chip will be described next February at the International Solid-State Circuits Conference in San Francisco. Intel said the 4-Mbit test vehicle proves the efficacy of OUM technology. "We have identified one cell structure and material combination that meets most of our desires. We'll now spend time to study in detail how this behaves and performs," Lai said. Credited for the ISSCC paper are researchers from Intel, Azalea and Ovonyx Inc. (Santa Clara, Calif.), which is helping Intel develop the fundamental OUM technology. The innards of the nonvolatile device will be first discussed at next month's International Electron Devices Meeting in Washington. There, Intel and Ovonyx are set to describe the structure, fabrication method, performance and reliability of the basic cell technology. An OUM nonvolatile memory cell uses a horizontal strip of chalco genide — a type of electrically conductive glass — connected to an electrode, forming a T shape. When a high current is applied through the electrode, the chalcogenide heats to more than 600°C in less than 10 nanoseconds, creating a region of amorphous glass with high resistance. When a lower current is applied, it heats up to less than 600°C and then cools to a crystalline state with lower resistance. Depending on the resistance level, the cell can be read as either a 1 or 0. "When you heat it high and then quench it quickly, it stays amorphous and the resistance is high. When you do an intermediate temperature, then you let it cool slower to a crystalline state of low resistance," Lai said. This principle of using differences in resistance is also being applied to another nascent nonvolatile memory known as magnetic RAM, which senses minute changes in the polarity of magnetic storage bits. MRAM is said to have many of the attributes of ovonic memories, such as high density, low voltage and low power. And MRAM promises even better read and write speeds of less than 50 nanoseconds and unlimited read/write endurance. Intel, however, believes it will be difficult to fabricate CMOS transistors for MRAM, and claims OUM will be easier to integrate with logic. Nonvolatile memory devices based on amorphous and crystalline technology have been the subject of study for more than 30 years, and had sparked the interest of Intel co-founder Gordon Moore in the company's early days. Since then, material scientists have learned how to prepare high-purity, thin-film chalcogenide materials to the point that they are used routinely for rewriteable CD and DVD disks, according to Lai. While Intel doesn't claim OUM is the perfect memory, OUM promises write performance of less than 100 ns and read/write endurance much higher than today's flash devices, which will be sufficient for most code and data storage applications, Intel said. Technology duel The duel between MRAM and OUM should get more heated in coming years. Motorola Inc., for example, plans to provide samples of MRAM devices in 2003, and hopes to begin production in 2004. IBM Corp. and Infineon Technologies also back MRAM, and NEC Corp. will present a paper at IEDM on a 0.10-micron MRAM device. Lai said Intel plans to create more OUM test vehicles for the 0.13- and 0.09-micron process generation, but hasn't determined at what point they will be ready for manufacture. Other companies investigating OUM include STMicroelectronics and British Aerospace, Lai said. OUM also has the potential to be used as a multilevel cell nonvolatile memory able to store more than one bit per cell. The differences between the high- and low-resistance states of OUM can be as much as 100-fold, opening the possibility that intermediary levels of resistance could be used to represent different bit states. Today, companies like Intel and Sandisk Corp. have devised flash memory chips that can sense four voltage levels in order to st ore two bits per cell. "In principle it can be done," Lai said, when asked about OUM's multilevel cell capability. "But it is not the goal at this time. We want to be very good at one bit per cell before we look at multi-level capability."