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Ambarella Adopts Cadence Clarity 3D Solver for AI Vision Processor Development	Jun. 01, 2020

Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development	May. 27, 2020

Cadence Delivers 10 New Verification IP Targeting Automotive, Hyperscale Data Center and Mobile Applications	May. 19, 2020

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput	May. 19, 2020

Cadence Expands Design IP Portfolio with 56G Long-Reach PAM4 SerDes on TSMC N7 and N6 Processes	May. 18, 2020

Cadence Reports First Quarter 2020 Financial Results	Apr. 21, 2020

Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput	Mar. 17, 2020

Cadence Elects Ita Brennan and Lewis Chew to Board of Directors	Mar. 17, 2020

Cadence Tensilica HiFi IP Accelerates AI Deployment with Support for TensorFlow Lite for Microcontrollers	Mar. 12, 2020

Cadence Collaborates with STMicroelectronics on Networking, Cloud and Data Center Electronics	Mar. 09, 2020

Dover Microsystems and Cadence Partner to Deliver Secure Processing with Silicon-Layer Security for Mission-Critical Applications	Mar. 09, 2020

Cadence Announces Industry's First Verification IP for PHY Covering Multiple Protocols	Feb. 26, 2020

Cadence Furthers Expansion in 5G RF Communications with Acquisition of Integrand	Feb. 14, 2020

Cadence Reports Fourth Quarter 2019 Financial Results	Feb. 13, 2020

Cadence Completes Acquisition of AWR Corporation from National Instruments	Jan. 16, 2020

Cadence Expands Collaboration with Broadcom for 5nm and 7nm Designs	Jan. 14, 2020

LC3 for Bluetooth LE Audio Now Available for Cadence Tensilica HiFi DSPs	Jan. 07, 2020

Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications	Dec. 10, 2019

Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation	Dec. 03, 2019

Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications	Dec. 03, 2019

New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging	Nov. 13, 2019

Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis	Nov. 06, 2019

Cadence Presented with Four 2019 TSMC Partner of the Year Awards	Oct. 31, 2019

Cadence Announces First-to-Market NVMe 1.4 Verification IP for High-Performance Computing	Oct. 22, 2019

Cadence Reports Third Quarter 2019 Financial Results	Oct. 22, 2019

Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology	Oct. 18, 2019

Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation	Oct. 18, 2019

Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology	Oct. 17, 2019

Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation "Hercules" CPU	Oct. 09, 2019

Adesto and Cadence Collaborate to Expand xSPI Ecosystem for Emerging IoT Devices	Oct. 02, 2019

Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies	Sep. 25, 2019

Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process	Aug. 06, 2019

Cadence Reports Second Quarter 2019 Financial Results	Jul. 23, 2019

Cadence Introduces Conformal Litmus to Deliver Fastest Path to Full-Chip Constraints and CDC Signoff	Jul. 22, 2019

Innovium Adopts the Cadence Innovus Implementation System for Its Highly Scalable Switch Silicon Family for Data Centers	Jul. 22, 2019

Cadence Delivers Portable Test and Stimulus Methodology and Library	Jul. 17, 2019

NSITEXE Accelerates Delivery of Data Flow Processor IP for Automotive and Industrial Applications Using the Cadence Digital Design Full Flow	Jul. 12, 2019

Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology	Jul. 03, 2019

Cadence Announces First-to-Market DisplayPort 2.0 Verification IP	Jun. 26, 2019

Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development	Jun. 19, 2019

Toshiba Selects Cadence Tensilica Vision P6 DSP as Image Recognition Processor for its Next-Generation ADAS Chip	Jun. 13, 2019

Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs	Jun. 05, 2019

Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program	Jun. 04, 2019

Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy	Jun. 04, 2019

NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs	May. 28, 2019

Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development	May. 28, 2019

Cadence Full-Flow Digital and Signoff Tools Optimized for New 7nm Arm Cortex-A77 CPU	May. 27, 2019

Thinci Deploys Full Cadence Verification Suite for AI Designs, Accelerating Project Schedule by Months	May. 23, 2019

Cadence Palladium and Protium Platforms Enable Innovium to Accelerate First-Pass Silicon Success for the Data Center Market	May. 20, 2019

New Cadence Tensilica Vision Q7 DSP IP Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets	May. 15, 2019

Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry's Advanced Process Technologies	May. 15, 2019

Cadence Tapes Out 112G Long-Reach SerDes IP on Samsung Foundry's 7LPP Process Technology	May. 15, 2019

Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology	May. 13, 2019

Cadence Delivers Smart JasperGold Formal Verification Platform	May. 07, 2019

Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology	Apr. 24, 2019

Cadence Reports First Quarter 2019 Financial Results	Apr. 23, 2019

Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design	Apr. 22, 2019

Cadence LPDDR4/4X Memory IP Subsystem Achieves ISO 26262 ASIL C Certification from SGS-TUV Saar Using TSMC 16FFC Process Technology	Apr. 17, 2019

Cadence Unveils Clarity 3D Solver, Delivering Unprecedented Performance and Capacity for System Analysis and Design	Apr. 03, 2019

Cadence Extends Cloud Leadership with New CloudBurst Platform for Hybrid Cloud Environments	Apr. 01, 2019

Cadence Digital Implementation and Parasitic Extraction Tools Enabled for Samsung Foundry Gate-All-Around Technology	Apr. 01, 2019

Cadence Collaborates with Northrop Grumman on Chip Design	Mar. 28, 2019

Cadence Announces Industry's First Verification IP for USB4	Mar. 14, 2019

Cadence Announces Complete, Silicon-Proven LPDDR5 IP Solution	Mar. 04, 2019

Cadence Tensilica Product Development Process and Software Products Certified for ISO 26262 ASIL D Compliance for Automotive Applications	Feb. 28, 2019

New Cadence Tensilica ConnX B20 DSP Boosts Performance by Up to 10X for Automotive Radar/Lidar and Up to 30X for 5G Communications	Feb. 26, 2019

Cadence Drives Release of Alternative EVS Codec Implementation in 3GPP	Feb. 25, 2019

Cadence Tools and IP Optimized for New Arm Neoverse N1 Platform to Advance the Cloud-to-Edge Infrastructure Market	Feb. 20, 2019

Cadence Reports Fourth Quarter and Fiscal Year 2018 Financial Results	Feb. 20, 2019

Cadence and Green Hills Software Announce Strategic Partnership to Accelerate Embedded System Safety and Security	Feb. 20, 2019

Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES	Feb. 15, 2019

Vayyar Selects Cadence Tensilica Vision DSP for Advanced Millimeter Wave 3D Imaging Radar Solution	Jan. 08, 2019

Optek Selects Cadence Tensilica HiFi 3 DSP for Bluetooth 5.0 Dual-Mode Audio/Voice SoC	Jan. 08, 2019

Cadence Timing Signoff Tools Enable MaxLinear to Deliver Industry's First 400Gbps PAM4 SoC on 16FF Process	Dec. 10, 2018

Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers	Nov. 14, 2018

Cadence Introduces the Tensilica HiFi 5 DSP, the First DSP Optimized for AI Speech and Audio Processing	Oct. 31, 2018

Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology	Oct. 24, 2018

Cadence Reports Third Quarter 2018 Financial Results	Oct. 23, 2018

Cadence Accelerates Next-Generation Cloud Datacenter Infrastructure with Industry's First Silicon-Proven, Long-Reach 7nm 112G SerDes IP	Oct. 22, 2018

Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing	Oct. 16, 2018

Cadence Verification Suite Enabled on Arm-Based HPC Datacenters	Oct. 16, 2018

Cadence to Demonstrate System and Automotive Solutions at Arm TechCon 2018	Oct. 10, 2018

Cadence Recognized with Four 2018 TSMC Partner of the Year Awards	Oct. 10, 2018

Cadence Expands its Cloud Portfolio with Delivery of TSMC OIP Virtual Design Environment	Oct. 03, 2018

Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies	Oct. 02, 2018

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation	Oct. 01, 2018

Cadence Launches New Tensilica DNA 100 Processor IP Delivering Industry-Leading Performance and Power Efficiency for On-Device AI Applications	Sep. 19, 2018

Cadence Achieves Amazon Web Services Industrial Software Competency Status for Its Cloud-Hosted Design Solution	Sep. 18, 2018

Cadence Full-Flow Digital Tool Suite Achieves GLOBALFOUNDRIES 22FDX Certification	Aug. 31, 2018

Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design	Aug. 14, 2018

Cadence Selected for DARPA ERI Machine Learning Contract to Accelerate Electronic Design Innovation	Jul. 24, 2018

Cadence Introduces Voltus-XP Technology with Extensive Parallelism, Up to 5X Acceleration, and Increased Capacity for Power Signoff at Advanced Nodes	Jul. 23, 2018

ArcSoft and Cadence Partner to Develop AI and Vision Applications	Jul. 13, 2018

Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification	Jul. 13, 2018

Cadence JasperGold Formal Verification Platform Enables Hitachi to Develop Measures for Fault Avoidance to Comply with IEC 61508 Series SIL 4 Requirements	Jul. 09, 2018

Cadence Full-Flow Digital and Signoff Tools Certified on Samsung Foundry's 7LPP Process Technology	Jul. 03, 2018

Rafael Micro Licenses Cadence Tensilica Fusion F1 DSP for Low-Power NB-IoT Modem IC	Jun. 28, 2018

Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0	Jun. 27, 2018

Cadence Delivers the First Broad Cloud Portfolio for the Development of Electronic Systems and Semiconductors	Jun. 25, 2018

Cadence Collaborates with Amazon Web Services to Deliver Electronic Systems and Semiconductor Design for the Cloud	Jun. 25, 2018

Cadence and Microsoft Collaborate to Facilitate Semiconductor and System Design on the Microsoft Azure Cloud Platform	Jun. 25, 2018

Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs	Jun. 01, 2018

Cadence Full-Flow Digital and Signoff Tools Certified on Samsung's 8LPP Process Technology	May. 23, 2018

Cadence Shortens Automotive Verification Closure with New Verification IP for UFS 3.0, CoaxPress, and HyperRAM	May. 03, 2018

Cadence Innovus Implementation System Speeds Development of New Realtek DTV SoC Solution	May. 03, 2018

Cadence Prototypes First IP Interface in Silicon for Preliminary Version of DDR5 Standard Being Developed in JEDEC	May. 01, 2018

Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation	May. 01, 2018

Cadence Supports New TSMC WoW Advanced Packaging Technology	May. 01, 2018

Cadence Reports First Quarter 2018 Financial Results	Apr. 24, 2018

Lip-Bu Tan on AI, China & Moore	Apr. 12, 2018

Cadence: Last Holdout for Vision + AI Programmability	Apr. 12, 2018

Cadence Boosts Vision and AI Performance with New Tensilica Vision Q6 DSP IP	Apr. 11, 2018

Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout	Apr. 11, 2018

Imec and Cadence Tape Out Industry's First 3nm Test Chip	Feb. 28, 2018

GEO Semiconductor Selects Cadence Tensilica Vision P5 DSP for Their Most Advanced Automotive Smart Viewing Camera Processor	Feb. 26, 2018

Software-Based GPS Receiver from Galileo Satellite Navigation Now Available on Cadence Tensilica Fusion F1 DSP	Feb. 20, 2018

Cadence Reports Fourth Quarter and Fiscal Year 2017 Financial Results	Feb. 01, 2018

Cadence Tensilica HiFi Audio DSP is the First DSP IP Core to Support Dolby Atmos for PCs	Jan. 08, 2018

Cadence Announces Availability of Industry's First PCI Express 5.0 Verification IP	Nov. 29, 2017

Cadence Appoints Anirudh Devgan as President	Nov. 20, 2017

HiSilicon Selects Cadence Tensilica Vision P6 DSP for its Latest Kirin 970 Mobile Application Processor	Nov. 06, 2017

Cadence to Expand High-Speed Communications IP Portfolio with Acquisition of nusemi inc	Nov. 02, 2017

Cadence Joules RTL Power Solution Enables Socionext to Accelerate Low-Power HEVC 4K/60p Video Codec Chip Development	Nov. 02, 2017

Cadence Reports Third Quarter 2017 Financial Results	Oct. 26, 2017

Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers	Oct. 24, 2017

Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX Process Technology	Oct. 13, 2017

Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform	Oct. 12, 2017

Cadence Achieves TUV SUD's First Comprehensive "Fit for Purpose - TCL1" Certification in Support of Automotive ISO 26262 Standard	Oct. 11, 2017

Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator	Oct. 10, 2017

Cadence Genus Synthesis Solution Enables Fuji Xerox to Improve Multi-Functional Printer SoCs Design Development	Oct. 02, 2017

Cadence DFM Signoff Solutions Achieve Qualification for Samsung 28nm FD-SOI/14nm/10nm Process Technologies	Sep. 25, 2017

Cadence Full-Flow Digital and Signoff Tools and Custom/Analog Tools Certified and Enabled for Intel 22FFL Process Technology	Sep. 19, 2017

Cadence Recognized with Three TSMC Partner of the Year Awards	Sep. 18, 2017

Cadence Introduces the Conformal Smart Logic Equivalence Checker	Sep. 14, 2017

Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation	Sep. 11, 2017

Cadence Tools and Flows Achieve Production-Ready Certification for TSMC's 12FFC Process	Sep. 11, 2017

Cadence Delivers Comprehensive IP Portfolio for TSMC 16FFC Automotive Design Enablement Platform	Sep. 07, 2017

Cadence Announces Legato Memory Solution, Industry's First Integrated Memory Design and Verification Solution	Sep. 07, 2017

Cadence Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU	Aug. 07, 2017

Cadence Announces Tensilica HiFi 3z DSP Architecture for Latest Mobile and Home Entertainment Applications	Jul. 25, 2017

Cadence Reports Second Quarter 2017 Financial Results	Jul. 25, 2017

Cadence Genus Synthesis Solution Enables Toshiba to Complete a Successful ASIC Tapeout with a 2X Logic Synthesis Runtime Improvement	Jul. 20, 2017

Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM	Jul. 18, 2017

Nagoya University and Cadence Collaborate to Port AUTOSAR-Compliant TOPPERS Automotive Kernel to Tensilica Processors and DSPs	Jul. 11, 2017

Cadence Expands Online Tool Access for ARM DesignStart Customers to Accelerate SoC Design Delivery	Jun. 20, 2017

Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node	Jun. 20, 2017

Cadence Announces VirtualBridge Adapter for Palladium Z1 Emulator to Accelerate Software Bring-Up Time by Up to Three Months	May. 31, 2017

New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board	May. 31, 2017

Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology	May. 25, 2017

Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung's 7LPP and 8LPP Process Technologies	May. 25, 2017