PCIe 3/2/1 SerDes PHY
I3C Prototyping Kit (HDK) Total IP in a Box
7 track High Density standard cell library at TSMC 40 nm
DDR multiPHY in GlobalFoundries (40nm, 28nm)
New Vidatronic CTO to Innovate and Scale Technology
Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem
Mixel Announces Immediate Availability of MIPI D-PHY v2.5 IP
Pyramid Vector Quantization and Bit Level Sparsity in Weights for Efficient Neural Networks Inference
Enabling Bluetooth Out-of-Band pairing through NFC
Towards Self-Driving Cars: MIPI D-PHY Enabling Advanced Automotive Applications
RISC-V Foundation moves to Switzerland
Shattering the neural network memory wall with Checkmate
Softbank looks for $2.76bn loan
© 2019 Design And Reuse
All Rights Reserved.
No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.
Visit our new Partnership Portal for more information.
Suppliers, list your IPs for free.