LPDDR4 multiPHY in TSMC (16nm)
PCIe 5.0 Controller
90nm FTP Non Volatile Memory for Standard CMOS Logic Process
64-bit microcontroller highly-optimized for area, efficient performance, and simplified integration into 64-bit SoCs
Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs
Expedera Introduces Its Origin Neural Engine IP With Unrivaled Energy-Efficiency and Performance
PLDA Introduces a Complete Line of PCIe IP for USB4, Enabling PCIe Support in USB4 Hubs, Hosts and Devices
A short primer on instruction set architecture
Building security into an AI SoC using CPU features with extensions
Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - Optimizing latency key factor
What is an ASIP?
Design IP Sales Grew 16.7% in 2020, Best Growth Rate Ever!
SiFive RISC-V Proven in 5nm Silicon
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