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Moto to link Power PC cores to C-5 net processor
By Loring Wirbel, EE Times
May 29, 2001 (6:43 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010522S0055
NEW ORLEANS — Motorola Inc.'s networking and computing systems group plans to integrate future versions of the C-5 network-processing core from C-Port Corp. with PowerPC RISC cores, particularly the new e500 Book E core, based on the G5 architecture. High-end network equipment designers are clamoring for a single device that could combine control-plane and data-path processors in a system-on-chip with an efficient shared-memory architecture, said C-Port president Larry Walker. At this week's Smart Networks Developers Forum here, Motorola executives stressed that there is more to this plan than showing off road maps for the PowerPC, PowerQuicc communications controller and C-5 network processor. Motorola must demonstrate an ability to offer simulation models of all its cores in a time frame that allows developers to work with cores before standard products are developed. Daniel Artusi, general manager of the networking and computing sy stems group, said in a keynote speech Monday (May 21) that Motorola should be judged in the coming year by its ability to quickly offer presilicon tools such as "virtual samples," entailing simulation models and the software necessary to enable their use in system-level design. Common threads Common threads are emerging in the PowerPC, PowerQuicc and C-5 programs. For example, even though the 8264 and 8266 PowerQuicc 2 processors that debuted this week feature on-chip PCI buses, Motorola will slowly wean itself from PCI and PCI-X, in favor of standardizing on RapidIO in all future processor releases. Walker said he was not aware until after Motorola's acquisition of C-Port just how broadly the company dominated the control-plane processor market with its PowerQuicc architecture. The most recent Cahners In-Stat analyses show Motorola holding an 80 percent market share in communication processors, largely due to the strength of its PowerQuicc line. Three new members of this family, w hich combines a PowerPC RISC chip with a 68000-based core, were introduced Monday (May 21): the MPC8264 with inverse-multiplexing-over-ATM functions; the MPC8265, with an integrated PCI bus; and the MPC8266 with both inverse muxing and PCI. The next generation of PowerQuicc, the MPC85xx family, will begin with a 266-MHz communication processor module on-chip, and integrate the PowerPC G5 core at a later date, Motorola executives said. It will have native 4-Gbit/second performance, according to the company. The subsequent MPC87xx Power Quicc family will offer 700-MHz G5 core performance from the beginning, and will be able to handle OC-12 (622-Mbit rates) with a 6-Gbit/s native capability. The standard PowerPC processor implementations already have moved to the G4 core, and Motorola introduced two new versions at its forum: the MPC7410 with AltiVec instruction extensions and full symmetric-multiprocessing support; and the MPC7440, a three-issue superscalar processor with an integrated Level 2 cac he. As Motorola moves to the fifth generation of Power PC, the G5, the architecture is targeted even more to the embedded space. The e500 Book E core will be described in detail on June 11 at the Embedded Processor Forum. But Brian Wilkie, vice president and general manager of the communication processor division, said that developers can expect a two-way superscalar core capable of out-of-order execution. The e5000 also will feature a branch unit with a 512-entry branch target buffer. The core will be integrated into a single-chip "core complex" along with on-chip switching fabrics for very advanced switching and routing designs, Wilkie said. At some point in this cycle, Motorola's Austin, Texas, teams will begin to work with C-Port's Massachusetts groups on unified C-5 and PowerQuicc designs. At least two generations of C-5 follow-ons, C-5 II and C-5 III, are planned, but the emphasis will be more on improving the efficiency of Internet Protocol packet forwarding than on rushing wire-speed support to 10 or 40 Gbits immediately. Walker said the likely candidates for on-chip buses are those that allow efficient shared-memory access to blocks of SRAM or magnetoresistive RAM. Also on the table are merged designs built on the StarCore and Polaris DSP cores. Ray Burgess, the vice president of strategy and marketing for Motorola's Semiconductor Products Sector, said a customized third-generation cellular platform could combine a StarCore 140, a communication module borrowed from PowerQuicc and one or many application processor units. In the meantime, system designs can make use of virtually all Motorola processing architectures. For example, media gateways supporting packetized voice can use StarCore DSPs for voice compression and packetization, PowerQuiccs for channel aggregation, PowerPCs for media gateway functions and C-5s for high-end packet routing, he said.